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3-channel, isolated, sigma-delta adc with spi data sheet ADE7912 / ade7913 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2013 analog devices, inc. all rights reserved. technical support www.analog.com features two ( ADE7912 ) or three ( ade7913 ) 24-bit isolated, - analog-to-digital converters (simultaneously sampling adcs) integrated iso power, isolated dc-to-dc converter on-chip temperature sensor 4-wire spi serial interface up to 4 ADE7912 / ade7913 devices clocked from a single crystal or an external clock synchronization of multiple ADE7912 / ade7913 devices 31.25 mv peak input range for current channel 500 mv peak input range for voltage channels reference drift: 10 ppm/c typical single 3.3 v supply 20-lead, wide-body soic package with 8.3 mm creepage operating temperature: ?40c to +85c safety and regulatory approvals (pending) ul recognition 5000 v rms for 1 minute per ul 1577 csa component acceptance notice #5a iec 61010-1: 400 v rms vde certificate of conformity din vde v 0884-10 (vde v 0884-10):2006-12 v iorm = 846 v peak applications shunt-based polyphase meters power quality monitoring solar inverters process monitoring protective devices isolated sensor interfaces industrial plcs typical applications circuit figure 1. general description the ADE7912 / ade7913 1 are isolated, 3-channel - adcs for polyphase energy metering applications using shunt current sensors. data and power isolation are based on the analog devices, inc., i coupler? technology. the ADE7912 features two 24-bit adcs, and the ade7913 features three adcs. the current adc provides a 67 db signal-to-noise ratio over a 3 khz signal bandwidth, whereas the voltage adcs provide a snr of 72 db over the same bandwidth. one channel is dedicated to measuring the voltage across a shunt when the shunt is used for current sensing. up to two additional channels are dedicated to measuring voltages, which are usually sensed using resistor dividers. one voltage channel can be used to measure the temperature of the die via an internal sensor. the ade7913 includes three channels: one current and two voltage channels. the ADE7912 has one voltage channel but is otherwise identical to the ade7913 . 1 protected by u.s. patents 5,952,849; 6,873,065; 7,075,329; 6,262,600; 7,489,526; 7,558,080. ot her patents are pending. neutral phase c isolation barrier load phase a earth phase b spi interface phase a ADE7912/ ade7913 ip im v1p vm v2p gnd mcu gnd iso_a 3.3v phase b ADE7912/ ade7913 ip im v1p vm v2p gnd mcu gnd iso_b 3.3v phase c ADE7912/ ade7913 ip im v1p vm v2p gnd mcu gnd iso_c 3.3v neutral line ADE7912/ ade7913 (optional) ip im v1p vm v2p gnd mcu gnd iso_n 3.3v 3.3v system microcontroller gnd mcu 11115-001
ADE7912/ade7913 data sheet rev. 0 | page 2 of 44 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? typical applications circuit ............................................................ 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? functional block diagrams ............................................................. 4 ? specifications ..................................................................................... 5 ? regulatory approvals (pending) ................................................ 7 ? insulation and safety related specifications ............................ 7 ? din v vde v 0884-10 (vde v 0884-10) insulation characteristics .............................................................................. 7 ? timing characteristics ................................................................ 8 ? absolute maximum ratings .......................................................... 10 ? thermal resistance .................................................................... 10 ? esd caution ................................................................................ 10 ? pin configuration and function descriptions ........................... 11 ? typical performance characteristics ........................................... 13 ? test circuit ...................................................................................... 15 ? terminology .................................................................................... 16 ? theory of operation ...................................................................... 18 ? analog inputs .............................................................................. 18 ? analog-to-digital conversion .................................................. 18 ? reference circuit ........................................................................ 20 ? crc of adc output values ..................................................... 20 ? temperature sensor ................................................................... 20 ? protecting the integrity of configuration registers .............. 21 ? crc of configuration registers............................................... 21 ? ADE7912/ade7913 status ....................................................... 21 ? insulation lifetime ..................................................................... 22 ? applications information .............................................................. 23 ? ADE7912/ade7913 in polyphase energy meters ................. 23 ? ADE7912/ade7913 clock ....................................................... 25 ? spi-compatible interface .......................................................... 26 ? synchronizing multiple ADE7912/ade7913 devices .......... 27 ? power management ........................................................................ 31 ? dc-to-dc converter................................................................. 31 ? magnetic field immunity ......................................................... 32 ? power-up and initialization procedures ................................. 33 ? hardware reset ........................................................................... 36 ? software reset ............................................................................. 36 ? power-down mode .................................................................... 36 ? layout guidelines ........................................................................... 37 ? ade7913 evaluation board ...................................................... 39 ? ADE7912/ade7913 version .................................................... 39 ? register list ..................................................................................... 41 ? outline dimensions ....................................................................... 44 ? ordering guide .......................................................................... 44 ? revision history 11/13revision 0: initial version
data sheet ADE7912/ade7913 rev. 0 | page 3 of 44 the ADE7912 / ade7913 include iso power?, an integrated, isolated dc - to - dc converter. based on the analog devices i coupler technology, the dc - to - dc converter provides the regulated power required by the first stage of the adcs at a 3.3 v input supply. iso power eliminates the need for an ex ternal dc - to - dc isolation block. the i coupler chip scale transformer technology is also used to isolate the logic signals between the first and second stages of the adc. the result is a small form factor, total isolation solution. the ADE7912 / ade7913 configuration and status registers are accessed via a bidirectional spi serial port for easy interfacing with microcontrollers. the ADE7912 / ade7913 can be clocked from a crystal or an external clock signal. to minimize the system bill of materials, the master ADE7912 / ade7913 can drive the clocks of up to three additional ADE7912 / ade7913 devices . multiple ADE7912 / ade7913 devices can be synchronized to sample at the same moment and provide coherent outputs. the ADE7912 / ade7913 are available in a 20- lead , pb - free , wide - body soic package with 8.3 mm creepage.
ADE7912/ade7913 data sheet rev. 0 | page 4 of 44 functional block diagrams figure 2. ADE7912 functional block diagram figure 3. ade7913 functional block diagram miso clkout/ dready cs sclk adc clock ldo im v1p v2p vm ref adc ldo ip gnd iso digital block and spi port xtal2 xtal1 gnd vdd iso gnd iso power isolation vdd gnd data data clock 1 2 8 3 4 5 6 7 10 9 19 20 12 18 17 16 15 14 13 11 adc isolation barrier temp sensor vref mosi data isolation ADE7912 11115-003 miso clkout/ dready cs sclk adc clock ldo im v1p v2p vm ref adc ldo ip gnd iso digital block and spi port xtal2 xtal1 gnd vdd iso gnd iso power isolation vdd gnd data data clock 1 2 8 3 4 5 6 7 10 9 19 20 12 18 17 16 15 14 13 11 adc isolation barrier temp sensor vref mosi data isolation ade7913 11115-002
data sheet ADE7912/ade7913 rev. 0 | page 5 of 44 specifications vdd = 3.3 v 10%, g n d = 0 v, o n - chip reference, xtal1 = 4 .096 mhz, t min to t max = ?40c to +85c , t a = 25c ( t ypical) . table 1 . parameter min typ max unit test conditions/comments analog inputs 1 pseudo differential signal voltage range between ip and im pins ? 31.25 + 31.25 mv peak im pin connected to gnd iso pseudo differential signal voltage range between v1p and vm pins and between v2p and vm pins ? 500 + 500 mv peak pseudo differential inputs between v1p and vm pins and between v2p and vm pins ; vm pin connected to gnd iso maximum vm and im voltage ? 25 + 25 mv crosstal k ? 90 db ip and im inputs set to 0 v ( gnd iso ) when v1p and v2p inputs at full scale ? 105 db v2p and vm inputs set to 0 v (gnd iso ) when ip and v1p inputs at full scale ; v1p and vm inputs set to 0 v (gnd iso ) when ip and v2p inputs at full scale input impedance to gnd iso (dc) ip, im, v1p, and v2p pins 48 0 k? vm pin 2 4 0 k? current channel adc offset error ? 2 mv voltage channels adc offset error ? 35 mv v2 c hannel applies to the ade7913 only adc offset drift over temperature ? 500 + 500 ppm /c v1 c hannel only gain error ? 4 + 4 % gain drift over temperature ? 1 35 + 1 35 ppm /c current c hannel ? 6 5 +6 5 ppm/c v1 and v2 c hannels ac power supply rejection, psr ? 90 db v dd = 3.3 v + 120 mv rms (50 hz/100 hz), ip = v1p = v2p = gnd iso dc power supply rejection, psr ? 80 db v dd = 3.3 v 330 mv dc, ip = 6.25 mv rms, v1p = v2p = 100 mv rms temperature sensor accuracy 5 c waveform sampling current channel 1 signal - to - noise ratio, snr 67 dbfs adc_freq = 8 khz, bw = 3300 hz 68 dbfs adc_freq = 8 khz, bw = 2000 hz 72 dbfs adc_freq = 2 khz, bw = 825 hz 74 dbfs adc_freq = 2 khz, bw = 500 hz signal - to - noise - and - distortion ratio, sinad 66 dbfs adc_freq = 8 khz, bw = 3300 hz 68 dbfs adc_freq = 8 khz, bw = 2000 hz 72 dbfs adc_freq = 2 khz, bw = 825 hz 73 dbfs adc_freq = 2 khz, bw = 500 hz total harmonic distortion, thd ? 79 dbfs adc_freq = 8 khz, bw = 3300 hz ? 78 dbfs adc_freq = 8 khz, bw = 2000 hz ? 82 dbfs adc_freq = 2 khz, bw = 825 hz ? 82 dbfs adc_freq = 2 khz, bw = 500 hz spurious - free dynamic range, sfdr 83 dbfs adc_freq = 8 khz, bw = 3300 hz 83 dbfs adc_freq = 8 khz, bw = 2000 hz 85 dbfs adc_freq = 2 khz, bw = 825 hz 85 dbfs adc_freq = 2 khz, bw = 500 hz voltage channels 1 signal - to - noise ratio, snr 72 dbfs adc_freq = 8 khz, bw = 3300 hz 74 dbfs adc_freq = 8 khz, bw = 2000 hz 77 dbfs adc_freq = 2 khz, bw = 825 hz 79 dbfs adc_freq = 2 khz, bw = 500 hz
ADE7912/ade7913 data sheet rev. 0 | page 6 of 44 parameter min typ max unit test conditions/comments signal-to-noise-and-distortion ratio, sinad 72 dbfs adc_freq = 8 khz, bw = 3300 hz 74 dbfs adc_freq = 8 khz, bw = 2000 hz 77 dbfs adc_freq = 2 khz, bw = 825 hz 78 dbfs adc_freq = 2 khz, bw = 500 hz total harmonic distortion, thd ?83 db fs adc_freq = 8 khz, bw = 3300 hz ?83 dbfs adc_freq = 8 khz, bw = 2000 hz ?85 dbfs adc_freq = 2 khz, bw = 825 hz ?85 dbfs adc_freq = 2 khz, bw = 500 hz spurious-free dynamic range, sfdr 86 dbfs adc_freq = 8 khz, bw = 3300 hz 86 dbfs adc_freq = 8 khz, bw = 2000 hz 87 dbfs adc_freq = 2 khz, bw = 825 hz 87 dbfs adc_freq = 2 khz, bw = 500 hz clkin 2 all specifications for clkin = 4.096 mhz input clock frequency, clki n 3.6 4.096 4.21 mhz clkin duty cycle 45 50 55 % xtal1 logic inputs input high voltage, v inh 2.4 v input low voltage, v inl 0.8 v xtal1 total capacitance 3 40 pf xtal2 total capacitance 3 40 pf clkout delay from xtal1 4 100 ns logic inputsmosi, sclk, cs input high voltage, v inh 2.4 v input low voltage, v inl 0.8 v input current, i in 15 na input capacitance, c in 10 pf logic outputsclkout/ dready and miso output high voltage, v oh 2.5 v i source = 800 a output low voltage, v ol 0.4 v i sink = 2 ma power supply for specified performance vdd pin 2.97 3.63 v minimum = 3.3 v ? 10%; maximum = 3.3 v + 10% i dd 12.5 19 ma bit 2 (pwrdwn_en) in config register cleared to 0 2.7 3 ma bit 2 (pwrdwn_en) in config register set to 1 50 a bit 2 (pwrdwn_en) in config register set to 1 and no clkin signal at xtal1 pin 1 see the terminology section for a definition of the parameters. 2 clkin is the internal clock of the ADE7912/ ade7913 . it is the frequency at which the part is clocked at the xtal1 pin. 3 xtal1/xtal2 total capacitances refer to the net capacitances on each pin. each capacitance is the sum of the parasitic capacit ance at the pin and the capacitance of the ceramic capacitor connected be tween the pin and gnd. see the ADE7912 / ade7913 clock section for more details. 4 clkout delay from xtal1 is the delay that occurs from a high to low transition at the xtal1 pin to a synchronous high to low t ransition at the clkout/ dready pin when clkout functionality is enabled.
data sheet ADE7912/ade7913 rev. 0 | page 7 of 44 r egulatory approvals (pending) the ADE7912 / ade7913 are pending approval by the organizations listed in table 2 . refer to table 8 and the insulation lifetime section for more information about the recommended maximum working voltages for specific cros s- isolation waveforms and insulation levels. table 2 . regulatory approvals ul csa vde recognized under ul 1577 component recognition program 1 approved under csa component acceptance notice 5a certified according to din vde v 0884 -10 2 (vde v 0884 - 10):2006 -12 single protection , 5000 v rms isolation voltage basic insulation per iec 6 1010 - 1, 400 v rms (564 v peak) maximum working voltage reinforced insulation, 846 v peak 1 in accordance with ul 1577, each ADE7912 / ade7913 is proof tested by applying an insulation test voltage 6000 v rms for 1 second (current leakage detection limit = 10 a). 2 in accordance with din v vde v 0884 - 10, each ADE7912 / ade7913 is proof tested by applying an insulation test voltage 1590 v peak for 1 second (partial discharge detection limit = 5 pc). the asterisk (*) marking branded on the component designa tes din vde v 0884 - 10 (vde v 0884 - 10):2006 - 12 approval. insulation and s afety related specifications table 3 . critical safety related dimensions and material properties parameter symbol value unit test conditions/comments rated dielectric insulation voltage 5000 v rms 1 - minute duration minimum external air gap (clearance) l(l01) 8.3 m m distance m easured from input terminals to output terminals, shortest distance through air along the pcb mounting plane, as an aid to pc b layout minimum external tracking (creepage) l(l02) 8. 3 m m measured from input terminals to output terminals, sh o rtest distance path along body minimum internal gap (internal clearance) 0.017 min m m insulation distance through insulation tracking resistance (comparative tracking index ) cti > 6 00 v iec 60112 isolation group i i material group (din vde 0110, 1/89, table 1) din v vde v 0884 - 10 (vde v 0884 - 10) i nsulation c haracteristics the ADE7912 / ade7913 are suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety data is ensured by the protective circuits. table 4 . vde characteristics description test conditions /comments symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 30 0 v rms i to i v for rated mains voltage 4 00 v rms i to ii i climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 846 v peak input -to - output test voltage, method b 1 v iorm 1.875 = v pd(m) , 100% production test, t ini = t m = 1 sec, partial discharge < 5 pc v pd(m) 159 2 v peak input -to - output test voltage, method a v pd(m) after environmental tests subgroup 1 v iorm 1.5 = v pd(m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc 1 273 v peak after input and/or safety test s subgroup 2 and subgroup 3 v iorm 1.2 = v pd(m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc 1018 v peak highest allowable overvoltage v iotm 6000 v peak surge isolation voltage v peak = 10 kv, 1.2 s rise time, 50 s, 50% fall time v iosm 6000 v peak safety limiting values maximum value allowed in the event of a failure (see figure 4 ) maximum junction temperature t s 150 c total power dissipation at 25 c p s 2.78 w insulation resistance at t s v io = 500 v r s >10 9 ?
ADE7912/ade7913 data sheet rev. 0 | page 8 of 44 figure 4 . thermal derating curve, dependence of safety limiting values on case temperature, per din v vde v 0884 - 10 timing characteristi cs vdd = 3.3 v 10%, gnd = 0 v, on - chip reference, clkin = 4.096 mhz, t min to t max = ?40c to +85c. table 5 . spi interface timing parameters parameter symbol min max unit cs to sclk positive edge t ss 50 ns sclk frequency 1 250 5 6 00 k hz sclk low pulse width t sl 80 ns sclk high pulse width t sh 80 ns data output valid after sclk edge t dav 80 ns data input setup time before sclk edge t dsu 70 ns data input hold time after sclk edge t dhd 20 ns data output fall time t df 20 ns data output rise time t dr 20 ns sclk rise time t sr 20 ns sclk fall time t sf 20 ns miso disable after cs rising edge t dis 5 40 ns cs high after sclk edge t sfs 0 ns 1 min imum and m ax imum specifications are guaranteed by design. 3.0 0 0.5 1.0 1.5 2.0 2.5 0 200 150 100 50 safe limiting power (w) ambient temperature (oc) 111 15-004
data sheet ADE7912/ade7913 rev. 0 | page 9 of 44 figure 5 . spi interface timing figure 6 . load circuit for timing specifications msb lsb lsb in intermediate bits intermediate bits t sfs t dis t ss t sl t df t sh t dhd t dav t dsu t sr t sf t dr msb in mosi miso sclk cs 11115-005 2ma i ol 800a i oh 1.6v to output pin c l 50pf 111 15-006
ADE7912/ade7913 data sheet rev. 0 | page 10 of 44 absolute maximum rat ings t a = 25c, unless otherwise noted. table 6 . parameter rating vdd to gnd ? 0.3 v to +3.7 v analog input voltage to gnd iso , i p, i m , v 1p , v 2 p, v m ? 2 v to +2 v reference input voltage to gnd iso ? 0.3 v to vdd + 0.3 v digital input voltage to gnd ? 0.3 v to vdd + 0.3 v digital output voltage to gnd ? 0.3 v to vdd + 0.3 v common - mode transients 1 - 100 kv/s to +100 kv/s operating temperature industrial range ? 40c to +85c storage temperature range ? 65c to +150c lead temperature (soldering, 10 sec) 2 260c 1 refers to common - mode transients across the insulation barrier. common - mode transients exceeding the absolute maximum ratings may cause latch - up or permanent damage. 2 analog devices recommends that reflow profiles used in soldering rohs compliant devices conform to j - std - 0 20 d.1 from jedec. refer to jedec for the latest revision of this standard . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the de vice at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja and jc are specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 7 . thermal resistance package type ja jc unit 20 - lead soic _ic 48.0 6.2 c/w esd caution table 8 . maximum continuous working voltage supporting a 50- year minimum lifetime 1 parameter max unit applicable certification ac voltage, bipolar waveform 564 v peak all certifications, 50 - year operation dc voltage, basic insulation 600 v peak 1 refers to the continuous voltage magnitude imposed across the isolation barrier. see the insulation lifetime section for more details.
data sheet ADE7912/ade7913 rev. 0 | page 11 of 44 pin configuration an d function descripti ons figure 7 . pin configuration table 9 . pin function descriptions pin no. mnemonic description 1 vdd iso isolated secondary side power supply. this pin provides access to the 3.3 v on - chip isolated power supply. do not connect external load circuitry to this pin. decouple this pin with a 10 f capacitor in parallel with a ceramic 100 nf capacitor using pin 2 , gnd iso . 2, 10 gnd iso ground reference of the isolated secondary side . the s e pin s provide the ground reference f or the analog circuitry. use the s e quiet ground refer ence s for all analog circuitry. these two pins are connected together internally. 3, 4, 5 v2p, v1p , vm analog inputs for the voltage channels. the voltage channels are used with the voltage transducers . v2p and v1p a re pseudo differential voltage inputs wi th a maximum signal level of 500 m v with respect to vm for specified operation. use these pins with the related input circuitry , as shown in figure 20. if v1p or v2p is not used, connect it to the vm pin. on the ADE7912 , connect the v2p pin to the vm pin because the v2p voltage channel is not available. the second voltage channel is available on the ade7913 only. 6, 7 im, ip analog inputs for the current channel. th e current channel is used with shu nts. im and ip are pseudo differential voltage inputs with a maximum differential level of 31.25 mv. use these pins with the related input circuitry , as shown in figure 20. 8 ldo 2.5 v output of analog low dropout (ldo) regulator . decouple this pin with a 4.7 f capacitor in parallel with a ceramic 100 nf capacitor to gnd iso , pin 10. do not connect external load circuitry to this pin. 9 ref voltage reference. this pin provides access to the on - chip voltage reference. the on - chip reference has a nominal value of 1.2 v. decouple this pin to gnd iso , pin 10 , with a 4.7 f capacitor in parallel with a ceramic 100 nf capacitor. 11, 20 gnd primary ground reference . 12 clkout/ dready clock output (clkout). when clkout functionality is selected (see the synchronizing multiple ADE7912 / ade7913 devices section for details), the ADE7912 / ade7913 generate a digital signal synchronous to the master clock at the xtal1 pin. use clkout to provide a clock to other ADE7912 / ade7913 devices on the board. data ready, active low ( dready ). when dready functionality is selected (see the synchronizing multiple ADE7912 / ade7913 devices section for details), the ADE7912 / ade7913 generate an active low signal synchronous to the adc output frequency. use this signal to start reading the adc outputs of the ADE7912 / ade7913 . 13 x tal1 master clock input. an external clock can be provided at this logic input. the clkout/ dready signal of another appropriately configured ADE7912 / ade7913 (see the synchronizing multiple ADE7912 / ade7913 devices section for details) can be provided at this pin. alternatively, a crystal with a maximum drive level of 0.5 m w and an equivalent series resistance (esr) of 20 ? can be connected across xtal1 and xtal2 to provide a clock source for the ADE7912 / ade7913 . the clock frequency for specified operation is 4.096 mhz, bu t lower frequencies down to 3.6 mhz can be used. see the ADE7912 / ade7913 clock section for more details . 14 x tal2 crystal , second input. a crystal with a maximum drive level of 0.5 m w and an esr of 20 ? can be connected across x tal2 and xtal1 to provide a clock source for the ADE7912 / ade7913 . 15 miso data out put for spi port. pull up this pin with a 10 k ? resistor ( s ee the ADE7912 / ade7913 clock section for details). 16 mosi data in put for spi port. 17 sclk serial clock input for spi port. all serial data transfers are synchronized to this clock (see the ADE7912/ ade7913 top view (not to scale) vdd iso 1 gnd iso 2 v2p 3 v1p 4 gnd 20 vdd 19 cs 18 sclk 17 vm 5 mosi 16 im 6 miso 15 ip 7 xtal2 14 ldo 8 xtal1 13 ref 9 clkout/dready 12 gnd iso 10 gnd 11 111 15-007
ADE7912/ade7913 data sheet rev. 0 | page 12 of 44 pin no. mnemonic description ade79 12 / ade7913 clock section). 18 cs chip select for spi port. 19 vdd primary supply voltage. this pin provides the supply voltage for the ADE7912 / ade7913 . maintain the supply voltage at 3.3 v 10% for specified operation. decouple this pin to gnd , pin 20, with a 10 f capacitor in parallel with a ceramic 1 00 nf capacitor.
data sheet ADE7912/ade7913 rev. 0 | page 13 of 44 typical performance characteristics figure 8 . current channel fft, 31.25 mv, 50 hz pseudo differential input signal, adc_freq = 8 khz, bw = 3300 hz figure 9 . current channel fft, 31.25 v, 50 hz pseudo differential input signal, adc_freq = 8 khz, bw = 3300 hz figure 10 . voltage channel v1 fft , 500 mv, 50 hz pseudo differential input signal, adc_freq = 8 khz, bw = 3300 hz figure 11 . voltage channel v1 fft , 500 v, 50 hz pseudo differential input signal, adc_freq = 8 khz, bw = 3300 hz figure 12 . voltage channel v2 fft , 50 0 mv, 50 hz pseudo differential input signal, adc_freq = 8 khz, bw = 3300 hz figure 13 . voltage channel v2 fft , 500 v, 50 hz pseudo differential input signal, adc_freq = 8 khz, bw = 3300 hz 20 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 500 1000 1500 2000 2500 3000 3500 4000 4500 11115-108 amplitude (db) frequency (hz) snr = 67.06db thd = ?78.71db sinad = 66.78db sfdr = 83.38db 0 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 500 1000 1500 2000 2500 3000 3500 4000 4500 11115-109 amplitude (db) frequency (hz) snr = 6.98db thd = ?20.04db sinad = 6.77db sfdr = 26.65db 20 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 500 1000 1500 2000 2500 3000 3500 4000 4500 11115-110 amplitude (db) frequency (hz) snr = 74.4db thd = ?80.05db sinad = 73.36db sfdr = 80.75db 0 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 500 1000 1500 2000 2500 3000 3500 4000 4500 11115-111 amplitude (db) frequency (hz) snr = 15.00db thd = ?28.08db sinad = 14.8db sfdr = 33.75db 20 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 500 1000 1500 2000 2500 3000 3500 4000 4500 11115-112 amplitude (db) frequency (hz) snr = 74.18db thd = ?80.44db sinad = 73.26db sfdr = 73.26db 0 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 500 1000 1500 2000 2500 3000 3500 4000 4500 11115-113 amplitude (db) frequency (hz) snr = 14.68db thd = ?27.97db sinad = 14.48db sfdr = 34.92db
ADE7912/ade7913 data sheet rev. 0 | page 14 of 44 figure 14 . cumulative histogram of the current channel adc gain temperature coefficient for temperatures between ? 40c and +25c figure 15 . cumulative histogram of the current channel adc gain temperature coefficient for temperatures between +25c and +85c figure 16 . cumulative histogram of the voltage channel v1 adc gain temperature coefficient for temperatures between ? 40c and +25c figure 17 . cumulative histogram of the voltage channel v1 adc gain temperature coefficient for temperatures between +25c and +85c figure 18 . cumulative histogram of the voltage channel v2 adc gain temperature coefficient for temperatures between ?40c and +25c figure 19 . cumulative histogram of the voltage channel v2 adc gain temperature coefficient for temperatures between +25c and +85c 100 0 10 20 30 40 50 60 70 80 90 11115-114 number of occurrences temperature coefficient (ppm/c) ?46 ?38 ?30 ?22 ?14 ?6 2 10 18 26 34 42 50 100 0 10 20 30 40 50 60 70 80 90 11115-115 number of occurrences temperature coefficient (ppm/c) ?56 ?48 ?40 ?32 ?24 ?16 ?8 0 8 16 24 32 40 100 0 10 20 30 40 50 60 70 80 90 11115-116 number of occurrences temperature coefficient (ppm/c) ?26 ?22 ?18 ?14 ?10 ?6 ?2 2 100 0 10 20 30 40 50 60 70 80 90 11115-117 number of occurrences temperature coefficient (ppm/c) ?28 ?26 ?24 ?22 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 100 0 10 20 30 40 50 60 70 80 90 11115-118 number of occurrences temperature coefficient (ppm/c) ?26 ?24 ?22 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 100 0 10 20 30 40 50 60 70 80 90 11115-119 number of occurrences temperature coefficient (ppm/c) ?28 ?26 ?24 ?22 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4
data sheet ADE7912/ade7913 rev. 0 | page 15 of 44 test circu it figure 20 . test circuit 11115-008 ADE7912 c / ade7913 c clkout/dready 19 miso 15 mosi 16 sclk 17 xtal1 13 xtal2 14 12 gnd 11 20 ts4148 ts4148 ts4148 ts4148 ts4148 150 ferrite 150 ferrite 150 ferrite 150 ferrite 150 ferrite ip im 33nf 33nf 33nf 100nf 4.7f 100nf 4.7f v1p vm v2p 7 6 4 5 3 gnd iso vdd iso 2 1 gnd iso ldo 10 8 9 ref gnd vdd same as in ADE7912 c / ade7913 c same as in ADE7912 c / ade7913 c tp4 tp5 22pf 22pf 4.096mhz 10f to mcu 100nf 330k 330k 330k 330k 330k 330k 1k 1k 1k 33nf 1k 33nf 1k 10f 100nf 3.3v tp3 tp1 tp2 cs 18 to mcu to mcu to mcu to mcu to mcu to mcu 18 19 ADE7912 b / ade7913 b xtal1 miso vdd 15 13 xtal2 14 17 16 12 gnd gnd 11 20 same as in ADE7912 c / ade7913 c vdd iso gnd iso v2p v1p vm im ip ldo ref gnd iso 1 2 3 4 5 6 7 8 9 10 mosi sclk clkout/dready cs 18 19 ADE7912 a / ade7913 a xtal1 miso vdd 15 13 xtal2 14 17 16 12 gnd gnd 11 20 same as in ADE7912 c / ade7913 c vdd iso gnd iso v2p v1p vm im ip ldo ref gnd iso 1 2 3 4 5 6 7 8 9 10 mosi sclk clkout/dready cs notes 1. ADE7912 x /ade7913 x = phase x ADE7912/ade7913, where x = a, b, or c. 3.3v 10k
ADE7912/ade7913 data sheet rev. 0 | page 16 of 44 terminology pseudo differential signal voltage range between i p and im, v1p and vm , and v2 p and v m pins the range represents the peak - to - peak pseudo differential voltage that must be applied to the adcs to generate a full - scale response when the im and vm pins are connected to gnd iso , pin 2 . the im and vm pins are connected to gnd iso using antialiasing filters (see figure 20 ). figure 21 illustrates the input voltage range between ip and im ; figure 22 illustrates the input voltage range between v1p and vm and between v2p and vm . figure 21 . pseudo differential inpu t voltage range between ip and im pins figure 22 . pseudo differential input voltage range between v1p and vm pins and between v2p and vm maximum vm and im voltage range the range represents the maximum allowed voltage at vm and im pins relative to gnd iso , pin 10 . crosstalk crosstalk represents leakage of signals, usually via capacitance between circuits. crosstalk is measured in the current channel by set ting the ip and im pins to gnd iso , pin 10 , supplying a full - scale alternate differential voltage between the v1p and vm pins and between the v2p and vm pins of the voltage channel , and measuring the output of the current channel. it is measured in the v1p voltage channel by setting the v1p and vm pins to gnd iso , pi n 10, supplying a full - scale alternate differential voltage at the ip and v2p pin , and measuring the output of the v1p channel. crosstalk is measured in the v2p voltage channel by setting the v2p and vm pins to gnd iso , pin 10 , supplying a full - scale alternate differential voltage at the ip and v1p pin s , and measuring the output of the v2p channel. the crosstalk is equal to the ratio between the grounded ad c output value and its adc full - scale output value. the adc outputs are acquired for 2 s ec . cross talk is expressed in decibels. input impedance to ground (dc) the input impedance to ground represents the impedance measured at each adc input pin (ip, im, v1p, v2p, and vm) with respect to gnd iso , pin 10 . differential input impedance (dc) the differential inpu t impedance represents the impe d a nce measured between the adc inputs: ip and im, v1p and vm , and v2p and vm ( ade7913 only) . adc offset error adc offset error is the difference between the average measured adc output code with both inputs connected to gnd iso and the ideal adc output code. the magni tude of the offset depends on the input range of each channel . adc offset drift over temperature the adc offset drift is the change in offset over temperature. it is measured at ? 40c, +25c , and +85c . the offset drift over temperature is computed as follow s: ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 25 85 25 25 85 , 25 40 25 25 40 max offset offset offset offset offset offset drift offset drift is expressed in nv/c. gain error the gain error in the adcs represents the difference between the measured adc output code (minus the of fset) and the ideal output code when the internal voltage reference is used (see the analog - to - digital conversion section) . the difference is expressed as a percentage of the ideal code. it represents the overall gain error of one current or voltage channel. ip im ip ? im 0v 0v 0v +31.25mv ?31.25mv +31.25mv ?31.25mv 111 15-009 +500mv ?500mv +500mv ?500mv v1p, v2p v1p ? vm, v2p ? vm vm 0v 0v 0v 111 15-010
data sheet ADE7912/ade7913 rev. 0 | page 17 of 44 gain drift over temperature this temperature coefficient includes the temperature variation of the adc gain and of the internal voltage reference. it repre - sents the overall temperature coefficient of one current or voltage channel. with the internal voltage reference in use, the adc gain is measured at ? 40c, +25c , and +85c. then the temperat ure coefficient is computed as follows: ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 25 85 25 25 85 , 25 40 25 25 40 max gain gain gain gain gain gain drift gain drift is measured in ppm /c. power supply rejection (psr) psr quantifies the measurement error as a percen tage of reading when the power supplies are varied. for the ac psr measurement, a reading at nominal supplies (3.3 v) is taken when the voltage at the input pins is 0 v . a second reading is obtained with the same input signal levels when an ac signal (120 mv rms at 50 hz or 100 hz) is introduced onto the supplies. any error introduced by this ac signal is expressed as a percentage of the reading ( p ower s upply r ejection r atio, psrr) . psr = 20 log 10 (psrr). for the dc psr measurement, a reading at nominal supplies (3.3 v) is taken when the voltage between the ip and im pins is 6.25 mv rm s , and the voltages between the v1p and vm pins and between the v2p and vm pins are 100 mv rms . a second reading is obtained with the same input signal levels when the power supplies are varied by 10%. any error introduced is expressed as a percentage of t he reading (psrr) . then psr = 20 log 10 (psrr). signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the spectral c ompo - nents are calculated over a 2 s ec window. the value for snr is expressed in decibels. signal -to - noise - and - distortion (sinad) ratio sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the spectral components are calculated over a 2 s ec window. the value for sina d is expressed in decibels. total harmonic distortion ( thd ) thd is the ratio of the rms sum of all harmonics ( excluding the noise components) to the rms value of the fundamental. the spectral components are calculated over a 2 s ec window. the value for thd is expressed in decibels. spurious - free dynamic range ( sfdr ) sfdr is the ratio of the rms value of the actual input signal to the rms value of the peak spurious component over the measurement bandwidth of the waveform samples. the spectral components are calculated over a 2 s ec window. the value of sfdr is expressed in decibel s relative to full scale, dbfs.
ADE7912/ade7913 data sheet rev. 0 | page 18 of 44 theory of operation analog inputs the ade7913 ha s three analog inputs: one current channel and two voltage channels. the ADE7912 does not include the second voltage channel. the current channel has two fully differential voltage input pins , ip and im , that accept a maxi - mum differential signal of 31.25 mv. the maximum v ip signal level is also 31.25 mv. the maxi - mum v im signal level allowed at the im input is 25 mv. fi gure 23 shows a schematic of the input for the current channel and its relation to the maximum im pin voltage. figure 23 . maxim um input level, current channel note that the current channel is used to sense the voltage across a shunt. in this case , one pole of the shunt becomes the ground of the meter (see figure 33 ) and, therefore, the current channel is used in a pseudo differential configuration, similar to the voltage channel configuration (see figure 24). the voltage channel has two pseudo differential, single - ended voltage input pins: v1p and v2p. these single - ended voltage inputs ha ve a maximum input voltage of 500 mv with respect to vm. the maximum signal allowed at the vm input is 25 m v. figure 24 shows a schematic of the voltage channel inputs and their relation to the maximum vm voltage. figure 24 . maximum input level, voltage channels analog - to - digital conversion the ADE7912 / ade7913 have three second - order - adcs. for simplicity, the block diagram in figure 25 shows a first - order - adc. the converter is composed of the - modulator and the digital low - pass fi lter, separated by the digital isolation block. figure 25 . first - order - adc a - modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling clock. in the ADE7912 / ade7913 , the sampling clock is equal to clkin/4 (1.024 mhz when clkin = 4.096 mhz). the 1 - bit dac in the feedback loop is driv en by the serial stream. the dac output is subtracted from the input signal. if the loop gain is high enough, the average value of the dac output (and, therefore, the bit stream) can approach that of the input signal level. for any given input value in a s ingle sampling interval, the data from the 1 - bit adc is virtually meaningless. a meaningful result is obtained o nly when a large number of samples is averaged. this averaging is completed in the second part of the adc, the digital low - pass filter, after th e data is passed through the digital isolators. by averaging a large number of bits from the modulator, the low - pass filter can produce 24 - bit data - words that are proportional to the input signal level. the - converter uses two techniques to achieve high resolu - tion from what is essentially a 1 - bit conversion technique. the first technique is oversampling. oversampling means that the signal is sampled at a rate (frequency) that is many times higher than the bandwidth of interest. for example, when clkin = 4.096 mhz, the sampling rate in the ADE7912 / ade7913 is 1.024 mhz, and the bandwidth of interest is 40 hz to 3.3 khz. over sampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. wit h the noise spread more thinly over a wider bandwidth , the quantization noise in the band width of interest is lowered, as shown in figure 26. however, oversam pling alone is not su fficient to improve the signal - to - noise ratio (snr) in the band of interest. for example, an oversampling factor of 4 is required to increase the snr by a mere 6 db (1 bit). to keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. noise shaping is the second te chnique used to achieve high resolution. in the - modulator, the noise is shaped by the integrator, which has a high - pass type response f or the quantization noise. the result is that most of the noise is at the higher frequencies where it can be removed by the digital low - pass filter. this noise shaping is shown in figure 26 . ip im v im v ip +31.25mv 0v v ip v ip = 31.25mv max peak v im = 25mv max ?31.25mv 111 15-033 v1p or v2p vm v m v 1 +500mv 0v v 1 v 1 = 500mv max peak v m = 25mv max ?500mv 111 15-034 24 digital low-pass filter r c + ? clkin/16 integrator v ref 1-bit dac latched comparator analog low-pass filter .....10100101..... + ? digital isolation isolation barrier 111 15-035
data sheet ADE7912/ade7913 rev. 0 | page 19 of 44 figure 26 . noise reduction due to oversampling and noise shaping in the analog modulator the bandwidth of interest is a function of the input clock fre - quency, the adc output frequency ( selectable by bits[5:4] (adc_freq) in the config register ; see the adc output v alues section for details) , and bit 7 (bw) of the config register. when clkin is 4.096 mhz and the adc output frequency is 8 khz, if bw is cleared to 0 ( the default value ) the adc bandwidt h is 3.3 khz. if bw is set to 1, the adc bandwidth is 2 khz. table 10 shows the adc output frequen - cies and the adc bandwidth function of the input clock (clkin) frequency. three cases are shown: one for clkin = 4.096 mhz, the typical clock input frequency value , one for clkin = 4.21 mhz, the maximum clock input frequency, and one for clkin = 3.6 mhz, the minimum clock input frequency. antialiasing fi lter figure 25 also shows an analog low - pass filter (rc) on the input to the adc. this filter is placed outside the ADE7912 / ade7913 , and its role is to prevent aliasing. aliasing is an artifact of all sampled systems , as shown in figu re 27 . aliasing refers to the frequency components in the input signal to the adc that are higher than ha lf the sampling rate of the adc and appear in the sampled signal at a frequency below half the sampling rate. frequency components above half the sampling freque ncy (also known as the nyquist frequency, that is, 512 khz) are imaged or folded back down below 512 khz. this happens with all ad cs, regardless of the architecture. in figure 27, only freque ncies near the sampling frequency of 1.024 mhz move into the band width of interest for me tering, that is, 40 hz to 3.3 khz or 40 hz to 2 khz. to attenuate the high frequency noise (near 1.024 mhz) and prevent the distortion of the band width of interest, a low - pass filer (lpf) must be introduced. it is recommended that one rc filter with a corn er frequency of 5 khz be used for the attenuation to be sufficiently high at the sampling frequency of 1.024 mhz. the 20 db per decade attenuation of this filter is usually sufficient to elimi nate the effects of aliasing . figure 27 . aliasing effects table 10 . adc output frequency and adc bandwidth as a function of clkin frequency clkin ( mhz ) bits adc_freq in config register adc output frequency (hz) adc bandwidth when bit bw i n config register cleared to 0 (hz) adc bandwidth when bit bw in config register set to 1 (hz) 4.096 00 8000 3300 2000 01 4000 1650 1000 10 2000 825 500 11 1000 412 250 4.21 00 8222 3391 2055 01 4111 1695 1027 10 2055 847 513 11 1027 423 256 3.6 00 7031 2900 1757 01 3515 1450 878 10 1757 725 439 11 878 362 219 noise signal noise signal 0 3.3 4 512 frequency (khz) high resolution output from digital lpf 1024 0 3.3 4 512 frequency (khz) 1024 digital filter shaped noise antialias filter (rc) sampling frequency 111 15-036 aliasing effects sampling frequency image frequencies 0 2 4 512 frequency (khz) 1024 111 15-037
ADE7912/ade7913 data sheet rev. 0 | page 20 of 44 adc transfer function all adcs in the ADE7912 / ade7913 produce 24 - bit signed output code s . with a full - scale input signal of 31.25 mv on the current channel and 0.5 v on the voltage channels , and with an internal refere nce of 1.2 v, the a dc output code is nominally 5,320,000 and usually varies for each ADE7912 / ade7913 around this value. the code from the adc can vary between 0x800000 (?8,388,608) and 0x7fffff (+8,388,607); this is equivalent to an input signal level of 49.27 mv on the current channel and 0.788 v on the voltage channels. however, for specified performance, do not exceed the nominal range of 31.25 mv for the current channel and 500 mv for the voltage channels; adc performance is guaranteed only for input signals within these limits. adc output values the adc output values are stored in three 24 - bit signed registers, iwv, v1wv, and v2wv, at a rate defined by bits[5:4] (adc_freq) in the config register. the output frequency is 8 khz (clkin/512), 4 khz (clkin/1024), 2 khz (clkin/2048), or 1 khz (clkin/4096) based on adc_freq being equal to 00, 01, 10, or 11, respec tively, when clkin is 4.096 mhz . the microcontroller reads the adc output registers one at a time or in burst mode. see the spi read operation and the spi read operation in burst mode sections for more information. reference circuit the nominal reference voltage at the ref pin is 1.2 v. this reference voltage is used for the adcs i n the ADE7912 / ade7913 . because the on - chip dc - to - dc converter cannot supply external loads, the ref pin cannot be overdri ven by a standalone external voltage reference. the voltage of the ADE7912 / ade7913 reference drifts slightly with tempera ture. table 1 lists the gain drift over temperature specification of each adc channel. this value includes the temperature variation of the adc gain , t ogether with the temperature variation of the internal voltage reference. crc of adc output values every output cycle, the ADE7912 / ade7913 compute the cyclic redundancy check (crc) of the adc output values stored in the iw v , v1wv, and v2wv registers. bits[5:4] (adc_freq) in the config register determine the adc output fr equency and, therefore, the update rate of the crc. the crc algorithm is based on the crc - 16- ccitt algorithm. the registers are introduced into a linear feedback shift register (lfsr) based generator one byte at a time, least significant byte first , as sho wn in figure 28 . each byte is then used with the most significant bit first . the 16 - bit result is written in the adc_crc register. figure 28 . crc calculation of adc output values figure 29 . lfsr generator used for adc_crc calculation figure 29 shows how the lfsr works. the iwv, v1wv, and v2wv register s form the [a 71 , a 70 ,, a 0 ] bits used by the lfsr. bit a 0 is bit 7 of the first register to enter the lfsr; bit a 71 is bit 16 of v2wv , the last register to enter the lfsr. the formulas that govern the lfsr are as follows: b i (0) = 1, where i = 0, 1, 2, , 15, the initial state of the bits that form the crc. bit b 0 is the least significant bit, and bit b 15 is the most significant bit . g i , where i = 0, 1, 2, , 15 are the coefficients of the generating polynomial defined by the crc - 16- ccitt algorithm as follows: g ( x ) = x 16 + x 12 + x 5 + 1 ( 1 ) g 0 = g 5 = g 12 = 1 ( 2 ) all other g i coefficients are equal to 0. fb ( j ) = a j ? 1 xor b 15 ( j ? 1) ( 3 ) b 0 ( j ) = fb ( j ) and g 0 ( 4 ) b i (j) = fb ( j ) and g i xor b i ? 1 ( j ? 1), i = 1, 2, 3, , 15 ( 5 ) equation 3 , equation 4 , and equation 5 must be repeated for j = 1, 2, , 72. the value written into the adc_crc register contains bit b i (72), i = 0, 1, , 15. the adc_crc register can be read by executing an spi register read access or as part of the spi burst mode read operation. see the spi read operation a nd the spi read operation in burst mode sections for more details. temperature sensor the ADE7912 / ade7913 contain a temperature sensor that is multiplexed with the v2p input of the voltage channel. bit 3 (temp_en) of the config register selects what the third adc of the ade7913 measures. if the temp_en bit is 0, its default value, the adc measures the voltage between the v2p and vm pins. if the temp_en bit is 1, the adc measures the tempera ture sensor. in th e case of the ADE7912 , the adc always measures the temperature sensor, and the state of the temp_en bit has no significance. in both the ADE7912 and the ade7913 , the conversion result is stored in the v2wv register. the time it + lfsr generator a 71 a 48 a 47 a 24 a 23 a 0 0 7 8 15 16 23 iwv register 0 7 8 15 16 23 0 7 8 15 16 23 v1wv register v2wv register 0 7 8 15 16 23 0 7 8 15 16 23 0 7 8 15 16 23 111 15-038 b 0 lfsr fb g 0 g 1 g 2 g 15 b 1 g 3 b 2 b 15 a 71 , a 70 ,...., a 2 , a 1 , a 0 111 15-039
data sheet ADE7912/ade7913 rev. 0 | page 21 of 44 takes for the temperature sensor measurement to settle after the temp_en bit is set to 1 is 5 ms. the expression used to calculate the temperature in the microcontroller is: temp = 8.72101 10 ? 5 ( v2wv + tempos 2 11 ) ? 306.47 where : temp is the temperature value measured in degrees celsius. the gain used to convert the bit informati on provided by the ADE7912 / ade7913 into degrees celsius has a default value of 8.72101 10 ? 5 c/lsb. the temperature measurement accuracy is 5c. tempos is the 8 - bit signed read - only register in which the temperature sensor offset is stored. the offset information is calculated during the manufacturing process, and it is stored with the opposite sign. for example, if the offset is 5, ?5 is written into the ADE7912 / ade7913 . one least significant bit (lsb) of the tem pos register is equivalent to 2 11 lsbs of the v2wv register. instead of using the default gain value, the gain can be calibrated as part of the overall meter calibration process. measure the temperature, temp, of every ADE7912 / ade7913 , read the v2wv register containing the temperature sensor reading of every a de7912 / ade7913 , and compute the gains as follows: temperature gain 11 2 2 + = tempos wv v temp ( 6 ) protecting the integ rity of configuratio n registers the configuration registers of the ADE7912 / ade7913 are either user accessible registers (config, emi_ctrl, sync_snap, counter0, and counter1) or internal registers . the internal registers are not user accessible, and they must remain at their default values. to protect the integrity of all configuration registers, a write protection mechanism is available. by default, the protection is disabled and the user accessib le configuration registers can be written without restriction. when the protection is enabled, no writes to any configuration register are allowed. the registers can always be read, without restriction, independent of the write protection state. to enable the protection, write 0xca to the 8 - bit lock register (address 0xa) . to disable the protection, write 0x9c to the 8 - bit lock register. it is recommended that the write protection be enabled after the config and emi_ctrl registers are initialized. if any us er accessible register must be changed, for example, during the synchronization process of multiple ADE7912 / ade7913 device s, disable the protection, change the value of the register, and then reenable the protection. crc of configuration registers every output cycle, the ADE7912 / ade7913 compute the crc of the config, emi_ctrl, and tempos registers, as well as bit 2 (ic_prot) of the status0 register, and bit 7 of the status1 register. the crc algorithm is called crc - 16- c c it t. the 16 - bit result i s written in the ctrl_crc register. the input registers to the crc circuit form a 64 - bit array that is introduced bit by bit into a n lfsr - based generator, similar to figure 28 and figure 29 , with one byte at a time, least significant byte first. each byte is then processed with the most significant bit first . the formulas that govern the lfsr are as follows: b i (0) = 1, where i = 0, 1, 2, , 15, the initial state of the bits that form the crc. bit b 0 is the least significant bit, and bit b 15 is the most significant bit . g i , where i = 0, 1, 2, , 15 are the coefficients of the generating polynomial defined by the crc - 16- ccitt alg orithm in equation 1 and equation 2 . fb ( j ) = a j ? 1 xor b 15 ( j ? 1) ( 7 ) b 0 ( j ) = fb ( j ) and g 0 ( 8 ) b i (j) = fb ( j ) and g i xor b i ? 1 ( j ? 1), i = 1, 2, 3, , 15 ( 9 ) equation 7 , equation 8 , and equation 9 must be repeated for j = 1, 2, , 64. the value written into the ctrl_crc register contains bit b i (64), i = 0, 1, , 15. because each ADE7912 / ade7913 has a particular tempos re gister value, each ADE7912 / ade7913 has a different ctrl_crc register default value. ADE7912 / ade7913 status the bits in the status0 and status1 registers of the ADE7912 / ade7913 characterize the state of the device. if the value of the ctrl_crc register changes, bit 1 (crc_stat) is set to 1 in the status0 register. this bit clears to 0 when the status0 register i s read. after the configuration registers are protected by writing 0xca into the lock register, bit 2 (ic_prot) in the status0 register is set to 1. it clears to 0 when the status0 register is read, and it is set back to 1 at the next adc output cycle. at power - up, or after a hardware or software reset, the ADE7912 / ade7913 signal the end of the reset period by clearing bit 0 (reset_on) to 0 in the status0 register. if the adc output values of iwv, v1wv , and v2wv are not read during an output cycle, bit 3 (adc_na) in the status1 register becomes 1. it clears to 0 when the s tatus1 register is read. the status0 and status1 registers can be read by executing an spi register read . status0 can also be read as part of the spi burst mode read operation. see the spi read operation and the spi read operation in burst mode sections for more information.
ADE7912/ade7913 data sheet rev. 0 | page 22 of 44 insulation lifetime all insulation struct ures eventually break down when subjected to voltage stress over a sufficiently long period of time. the rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. in addition to the testing pe rformed by the regulatory agencies, analog devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADE7912 / ade7913 devices. analog devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. acceleration factors for several operating conditions are determined. th ese factors allow calculation of the time to failure at the actual working voltage. the values shown in table 8 summarize the maximum csa/vde approve d working voltage for 50 years of service life for a bipolar ac operating condition. in many cases, the approved working voltage is higher than the 50 - year service life voltage. operation at these high working voltages can lead to shortened insulation life in some cases. the insulation lifetime of the ADE7912 / ade7913 devices depends on the voltage waveform type imposed across the isolation barrier. the i coupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. fig ure 30 , figure 31 , and figure 32 illustrate these different isolation voltage waveforms. bipolar ac voltage is the most stringent environment. the goal of a 50 - year operating lifetime under the bipolar ac condition determines the max imum working voltage recommended by analog devices. in the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. this allows operation at higher working voltages while still achieving a year service life. t he working v oltages listed in table 8 can be applied while maintaining the 50 - year minimum lifetime, provided that the voltage conforms to either the unipolar ac o r dc voltage case. treat any cross - insulation voltage waveform that does not conform to figure 31 or figure 32 as a bipolar ac waveform , and limit its peak voltage to the 50 - year lifetime voltage value listed in table 8 . the voltage shown in figure 31 is shown as sinusoidal for illustration purposes only . it is meant to represent any voltage waveform varying between 0 v and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0 v. figure 30 . bipolar ac waveform figure 31 . unipolar ac waveform figure 32 . dc waveform rated peak voltage 0v 111 15-040 rated peak voltage 0v 111 15-041 rated peak voltage 0v 111 15-042
data sheet ADE7912/ade7913 rev. 0 | page 23 of 44 a pplications i nformation ADE7912 / ade7913 in polyp hase energy meters the ADE7912 / ade7913 are designed for use in 3 - phase energy metering systems in which two, three , or four ADE7912 / ade7913 devices are managed by a master device containing an spi interface, usually a microcontroller . figure 33 . phase a ADE7912 / ade7913 current and voltage sensing figure 33 shows the phase a of a 3 - phase energy meter. the phase a current , i a , is sensed with a shunt. a pole of the shunt is connected to the im pin of the ADE7912 / ade7913 and becomes the ground , gnd iso (pin 10), of the isolated side of the ADE7912 / ade7913 . the phase a to neutral voltage , v an , is sensed with a resistor divider , and the vm pin is also connected to the im and gnd iso pins. note that the voltages measured by the adcs of the ADE7912 / ade7913 are opposite to v an and i a , a classic approach in single - phase metering. the other ADE7912 / ade7913 devices that monitor phase b and phase c are connected in a similar way. the v2p voltage channel is intended to measure an auxiliar y voltage , and it is available only on the ade7913 . if v2p is not used, as is the case of the ADE7912 , connect v2p to vm . figure 34 . neutral line and neutral to earth voltage monitoring with the ADE7912 / ade7913 figure 34 shows how the ADE7912 / ade7913 inputs are connected when the neutral line of a 3 - phase system is monitored. the neutral current is sensed using a shunt and the voltage across the shunt is measured at the fully differential inputs , ip and im. the earth to neutral voltage is sensed with a voltage divider at the single - ended inputs , v1p and vm. figure 35 shows a block diagram of a 3 - phase en ergy meter that uses three ADE7912 / ade7913 devices and a microcontroller. the neutral current is not monitored in this exa mple . one 4.096 mhz crystal provides the clock to the ADE7912 / ade7913 that senses the phase a current and voltage. the ADE7912 / ade7913 devices that sense the phase b and phase c currents and voltages are clocked by a signal generated at the cl kout / dready pin of the ADE7912 / ade7913 that is placed to sense the phase a current and voltage. as an al ternative configura tion, the microcontroller can generate a 4.096 mhz clock to all ADE7912 / ade7913 devices at the xtal1 p in (see figure 36). note that the xtal1 pin can receive a clock with a frequency within the 3.6 mhz to 4.21 mhz range, as specified in table 1 . the microcontroller uses the spi port to communicate with the ADE7912 / ade7913 dev ices . three of its i/o pins, cs_a, cs_b , and cs_c , are used to generate the spi cs signals. the sclk, mosi , and miso pins of the microcontroller are directly conn ected to the corresponding sclk, mosi , and miso pins of each ADE7912 / ade7913 device ( see figure 39 ) . to simplify figure 35 to figure 38 , the se connections are not shown. figure 35 . 3- phase energy meter using three ADE7912 / ade7913 devices neutral phase a phase a ADE7912/ ade7913 ip im gnd iso v1p vm i a v an 111 15-0 1 1 neutral earth neutral line ADE7912/ ade7913 ip im v1p vm gnd iso i n v n 111 15-012 11115-013 cs_a cs_b cs_c sclk mosi miso i/o microcontroller neutral phase c isolation barrier phase a phase b phase a ADE7912/ade7913 phase b ADE7912/ade7913 phase c ADE7912/ade7913 ip im v1p vm v2p gnd mcu gnd iso_a xtal2 xtal1 sclk mosi miso cs ip im v1p vm v2p gnd mcu gnd iso_b xtal2 xtal1 sclk mosi miso cs ip im v1p vm v2p gnd mcu gnd iso_c xtal2 xtal1 sclk mosi miso cs load 4.096mhz crystal clkout/ dready clkout/ dready clkout/ dready
ADE7912/ade7913 data sheet rev. 0 | page 24 of 44 figure 36 . microcontroller generating clock to three ADE7912 / ade7913 devices in figure 36 , t he clkout/ dready pin of the ADE7912 / ade7913 that is used to sense the phase c current and voltage is connected to the i/o pin of the microcontroller. clkout/ dready provides an active low pulse for 64 clkin cycles (15.625 s at clkin = 4.096 mhz) when the adc conversion data is available. it signals when the adc outputs of all ADE7912 / ade7913 devices become available and when the microcontroller starts to read them. see the synchronizing multiple ade7913 devices section for more information about synchronizing multiple ADE7912 /a de7913 devices . at power - up, or after a hardware or software reset, follow the procedure described in the power - up procedure for systems with multiple devices that use a single crystal section or the power - up procedure for systems with multiple devices that use clock generated from microcontroller section to ensure that the ADE7912 / ade7913 devices function appropriately. the configuration of an energy meter using four ADE7912 / ade7913 devices is similar , shown in figure 37 . the microcontroller uses an additional i/o pin, cs_n, to generate the spi cs signal to the ADE7912 / ade7913 device that is monitoring the neutral current. figure 37 . 3- phase energy meter using four ADE7912 / ade7913 devices figure 38 shows an energy meter using two ADE7912 / ade7913 devices in a delta configuration . the meter ground is on th e phase b line. one ADE7912 / ade7913 device measures phase a current and phase a to phase b voltage. a s econd ADE7912 / ade7913 device measures phase c current and phase c to phase b voltage. phase b current and phase a to phase c volt age are computed by the system microcontroller. 11115-014 cs_a cs_b cs_c sclk mosi miso clk i/o microcontroller neutral phase c isolation barrier phase a phase b phase a ADE7912/ade7913 phase b ADE7912/ade7913 phase c ADE7912/ade7913 ip im v1p vm v2p gnd mcu gnd iso_a xtal2 xtal1 sclk mosi miso cs ip im v1p vm v2p gnd mcu gnd iso_b xtal2 xtal1 sclk mosi miso cs ip im v1p vm v2p gnd mcu gnd iso_c xtal2 xtal1 sclk mosi miso cs load clkout/ dready clkout/ dready clkout/ dready 11115-015 cs_a cs_b cs_c cs_n sclk mosi miso i/o microcontroller neutral phase c isolation barrier phase a phase b phase a ADE7912/ade7913 phase b ADE7912/ade7913 phase n ADE7912/ade7913 ip im v1p vm v2p gnd mcu gnd iso_a xtal2 xtal1 sclk mosi miso cs ip im v1p vm v2p gnd mcu gnd iso_b xtal2 xtal1 sclk mosi miso cs ip im v1p vm v2p gnd mcu gnd iso_n xtal2 xtal1 sclk mosi miso cs load earth phase c ADE7912/ade7913 ip im v1p vm v2p gnd mcu gnd iso_c xtal2 xtal1 sclk mosi miso cs 4.096mhz crystal clkout/ dready clkout/ dready clkout/ dready clkout/ dready
data sheet ADE7912/ade7913 rev. 0 | page 25 of 44 figure 38 . 3- phase meter using two ADE7912 / ade7913 devices in delta configuration figure 39 . spi connections between three ADE7912 / ade7913 devices and a microcontroller ADE7912 / ade7913 clock provide a digital clock signal at the xtal 1 pin to clock the ADE7912 / ade7913 . the frequency at which t he ADE7912 / ade7913 are clocked at xtal1 is called clkin. the ADE7912 / ade7913 are specified for clkin = 4.096 mhz, but frequencies between 3.6 mhz and 4.21 mhz are acceptable. alternatively, a 4.096 mhz crystal with a typical drive level of 0.5 m w and an equivalent series resistance (esr) of 20 can be connected across the xtal 1 and xtal 2 pins to provide a clock source for the ADE7912 / ade7913 ( see figure 40). the total capacitance , tc , at the xtal1 and xtal2 pins is tc = c1 + cp1 = c2 + cp2 w here: c1 and c2 are the ceramic capacitors between xtal1 and gnd and between xtal2 and gnd , respect ively . cp1 and cp2 are the parasitic capacitors of the wires connecting the crystal to the ADE7912 / ade7913 . the load capac itance , lc , of the crystal is equal to half the total capacitance , tc , because it is the capacitance of the series circuit composed by c1 + cp1 and c2 + cp2. 2 2 2 tc cp2 c2 cp1 c1 lc = + = + = therefore, the value of the c1 and c2 capacitor s as a function of the loa d capacitance of the crystal is c1 = c2 = 2 lc ? cp1 = 2 lc ? cp2 in the case of the ADE7912 / ade7913 , the typical total capacitance , tc , of the xtal1 and xtal2 pins is 40 pf (see table 1 ) . select a crystal with a load capacitance of pf 20 2 = = tc lc assuming the parasitic capacitances , cp1 and cp2 , are equal to 20 pf, select capacitors c1 and c2 equal to 20 p f. figure 40 . crystal circuitry 11115-016 cs_a cs_c sclk mosi miso i/o microcontroller 4.096mhz crystal phase c isolation barrier phase a phase b ip im v1p vm v2p gnd mcu gnd iso_c ip im v1p vm v2p gnd mcu gnd iso_a xtal2 xtal1 sclk mosi miso cs xtal2 xtal1 sclk mosi miso cs phase a ADE7912/ade7913 phase c ADE7912/ade7913 clkout/ dready clkout/ dready load ADE7912/ ade7913 phase a ADE7912/ ade7913 phase b ADE7912/ ade7913 phase c sclk mosi miso sclk mosi miso sclk mosi miso cs_a cs_b sclk mosi miso cs_c microcontroller cs cs cs n? vdd 111 15-017 ADE7912/ ade7913 xtal1 xtal2 c1 c2 cp1 cp2 tc tc 111 15-018
ADE7912/ade7913 data sheet rev. 0 | page 26 of 44 spi - compatible interface the spi of the ADE7912 / ade7913 is the slave of the communication and consists of four pins: sclk, mosi, miso , and cs . the serial clock for a data transfer is applied at the sclk logic input. all data transfer operations synchronize to the serial clock. data shifts into the ADE7912 / ade7913 at the mosi logic input on the falling edge of sclk , and the ADE7912 / a de7913 sample the data on the rising edge of sclk. data shifts out of the ADE7912 / ade7913 at the miso logic output on the falling edge of sclk and can be sampled by the master device on the r ising edge of sclk. the most significant bit of the word is shifted in and out first. the maximum and minimum serial clock frequenc ies supported by this interface are 5 .6 mhz and 250 k hz , respectively . miso stays in high impedance when no data is transmitted from the ADE7912 / ade7913 . at power - up or during hardware or software reset, the microcontroller reads the status0 register to detect when bit 0 ( reset_on ) clears to 0. see figure 39 fo r details of the connection s between the spi ports of t hree ADE7912 / ade7913 devices and a microcontroller containing an spi interface. the cs logic input is the chip select input. drive the cs input low for the entire data transfer operation. bringing cs high during a data transfer operation leaves the ADE7912 / ade7913 register that is the object of the data transfer unaffected, but aborts the transfer and places the serial bu s in a high impedance state. a new transfer can then be initiated by returning the cs logic input to low. figure 41 . spi read operation of an 8 - bit register figure 42 . spi read operation in burst mode figure 43 . spi write operation 0 7 6 1 0 register value sclk mosi cs miso 1 0 addr[4:0] 111 15-019 sclk mosi cs miso 1 0 0 0 0 0 0 0 iwv cnt_snapshot 23 0 15 0 111 15-020 sclk mosi cs 7 6 1 0 register value 0 0 0 addr[4:0] 111 15-021
data sheet ADE7912/ade7913 rev. 0 | page 27 of 44 spi read operation the read operation using the ADE7912 / ade7913 spi interface is initiate d when the master sets the cs pin low and begins sending one command byte on the mosi line. the master places data on the mosi line starting with the first high to low transition of sclk. the bit composition of the command byte is shown in table 1 1 . bits[ 1:0 ] are dont care bits , and they can have any value. the examples presented throughout this section show them set to 00. bit 2 ( read_en ) determines the type of the operation. for a read, read_en must be set to 1. for a write, read_en must be cleared to 0. bits[ 7:3 ] (addr) represent the address of the register to be read or written. the ADE7912 / ade7913 spi samples data on the low to high transitions of sclk. after the ADE7912 / ade7913 device receives the last bit of the command byte on a low to high transition of sclk, it begins to transmit its contents on the miso line when the next sclk high to low transition occurs; thus, the master can sample the da ta on a low to high sclk transition. after the master receives the last bit, it sets the cs and sclk lines high and the communication ends. the data lines, mosi and miso, go into a high impedance state. figure 41 shows an 8 - bit register read operation ; 16 - bit and 32 - bit registers are read in the same manner. table 11 . command byte for spi read/write operations bit location bit name description 1:0 reserved these bits can have any value. 2 read_en set this bit to 1 if a spi read operation is executed. clear this bit to 0 if a spi write operation is executed. 7:3 addr address of the register to be read or written. spi read o peration in b urst m ode all ADE7912 / ade7913 output registers ( i w v, v 1 w v, v 2 w v, adc_crc, status 0 , and cnt_snap shot ) can be read in one of two ways : one register at a time (see the spi read operation section) or by reading multiple consecutive regis ters simultaneously in burst mode. burst mode is initiate d when the master sets the cs pin low and begins sending the com mand byte ( see table 11) on the mosi line with bits[ 7:3 ] (addr) set to the i wv register address , 00000 . this means a command byte set to 0x04. the master places data on the mosi line starting with the first high to low transition of sclk. the spi of the ADE7912 / ade7913 samples data on the low to high transitions of sclk. after the ADE7912 / ade7913 device receives the last bit of the command byte on a low to high transition of sclk, it begins to transmit the 24 - bit i wv register on the miso line when the next sclk high to low transition occurs; thus, the master can sample the data on a low to high sclk transition. after the ma ster receives the last bit of the i wv register , the ADE7912 / ade7913 device s ends v1 wv , which is placed at the next location , and continues in this manner until the master sets the cs and sclk lines high and the communication ends. the data lines, mosi and miso , go into a high impedance state. see figure 42 for details of the spi read operation in burst mode. i f a register does not need to be read, for example, the 16 - bit cnt_snap shot register, the master sets the cs and sclk l ines high after the status 0 register is received. if the i wv register , for example, i s not required, but v1 wv is, set the addr bits to the v1 wv address, 00001, in the command byte , and execute the burst mode operation. spi write operation the spi write operation is initiate d when the master sets the cs pin low and begins sending one command byte (see table 11) . bit 2 ( read_en ) must be cleared to 0. the master places data on the mosi line starting with the first high to low transition of sclk. the spi of the ADE7912 / ade7913 samples data on the lo w to high transitions of sclk. next, the master sends the 8 - bit value of th e register without losing any sclk cycle s . after the last bit is transmitted, at the end of the sclk cycle, the master set s the cs and sclk lines high and the communication ends. the data lines, mosi and miso, go into a high imped - ance state. see figure 43 for details of the spi write operation. note that the spi write operation can execute 8 - bit writes only . the 16 - bit synchronization counter register (composed of counter0 and counter1) is wri tten by executing the write operation twice: the less significant byte is written first , followed by the most significant byte. see the synchronizing multiple ADE7912 / ade7913 devices section for details on the functionality controlled by the synchronization counter register. because the ADE7912 / ade7913 do not need to acknowledge a write command in any way, this operation can be broadcast to multiple ADE7912 / ade7913 devices when the same register must be initialized with the same value. after executing a write operation, it is recommended to read back the register to ensure that it was initialized correctly. synchronizing multip le ADE7912 / ade7913 devices the ADE7912 / ade7913 allow the user to sample all currents and voltages simultaneously and to provide coherent adc output samples, which is a highly desired feature i n polyphase metering systems. the emi reduction scheme managed by the emi_ctrl register (see the dc - to - dc converter section for details) requires that the ADE7912 / ade7913 provide coherent samples. the ADE7912 / ade7913 in polyphase energy meters section describes how a polyphase energy meter containing multiple ADE7912 / ade7913 devices can use one crystal to clock all the ADE7912 / ade7913 devices . at power - up, only one ADE7912 / ade7913 device is clocked from the crystal , as the other devices are set to receive the clock from the clkout/ dready pin of the first ADE7912 / ade7913 device . t his pin has dready
ADE7912/ade7913 data sheet rev. 0 | page 28 of 44 functional ity enable d by default. in figure 35, figure 37 , and figure 38 , the ADE7912/ ade7913 device on phase a is clocked from the crystal , and the clkout/ dready pin generates the dready signal. th e other ADE7912 / ade7913 devices are clocked by the dready signal because the clkout signal has not yet been receiv ed by their xtal1 pin s . the microcontroller enables clkout functionality when bit 0 (clkout_en) is set to 1 in the config register. this operation ensures that the other ADE7912 / ade7913 devices in the system receive the same clock as the ADE7912 / ade7913 on phase a and that all adcs within all ADE7912 / ade7913 devices in the system sample data at the same e xact moment. as an alternative to using one crystal, the microcontroller can generate a clock signal to the xtal1 pins of every ADE7912 / ade7913 , ensuring precise adc sampling synchronization (see figure 36) . to configure all ADE7912 / ade7913 devices in an energy meter to provide coherent adc output samples, that is , samples obtained in the same output cycle, all ADE7912 / ade7913 devices must have the same adc output frequency and the ou tputs must be synchronized . bits[ 5 :4 ] (adc_freq) in the config register select the adc output frequency ; therefore, they must be initialized to the same value (see the adc output value s section for more details). to synchronize the adc output s , that is , to set all ADE7912 / ade7913 devices to generate adc outputs at the same exact moment, after power - up, the microcontroller must broadcast a write to the 8 - bit sync_snap register with the value 0x01. all ade791 2 / ade7913 devices then start a new adc output period simultane ously when bit 0 ( sync ) of the sync_snap register is written. the sync bit clears itself to 0 after one clkin cycle. as shown in figure 35, figure 37 , and figure 38 , the clkout/ dready pin of one ADE7912 / ade7913 is connected to an i/o input of the microcontroller. this ADE7912 / ade7913 device has bit 0 (clkout_en) in the conf ig register set to the default value, 0 , to enable the dready functionality. when the adc output period starts, the clkout/ dready pin goes low for 64 clkin cycles (15.625 s when clkin = 4.096 mhz) , signaling that all adc outputs from all ADE7912 / ade7913 devices are available and the microcontroller must start reading them. it is recommended that the spi read in burst mode be used to ensure that all data is read in the shortest amount of time. t he ADE7912 / ade7913 contain an internal 1 2 - bit counter that functions at the clkin frequency. the counter is synchron ized with the adc output period and the clkout/ dready pin . when a ne w output period starts, the counter starts decreasing from a value determined by bits[ 5 :4 ] (adc_freq) in the config register. table 12 shows these values. table 12 . counter initial values as a function of adc_freq bits bits[5:4] (adc_freq) in config register adc output frequency (khz) counter c 0 init ial value (clkin = 4.096 mhz) counter c 0 initial value as a function of clkin 00 8 511 1 8000 ? clkin 01 4 1023 1 4000 ? clkin 10 2 2047 1 2000 ? clkin 11 1 4095 1 1000 ? clkin
data sheet ADE7912/ade7913 rev. 0 | page 29 of 44 figure 44 . synchronizing phase a and phase b ADE7912 / ade7913 devices w ith phase c ADE7912 / ade7913 figure 45 . cnt_snapshot register the 8 - bit sync_snap register latches the value of the counter when it is written with 0x02 , that is, bit 1 ( snap ) set to 1 . a broadcast write to all ADE7912 / ade7913 devices ensures that all the counters of every ADE7912 / ade7913 are latched at the same moment. the snap bit clears itself to 0 after one clkin cycle. the values of the cou nters offer a measu re of the adc output synchronization across all ADE7912 / ade7913 devices . ideally, the values should be perfectly equal , indicating that all ADE7912 / ade7913 devices are fully synchronized. in reality, due to the uncertainty be tween the spi clock generated by the microcontroller and the ADE7912 / ade7913 clkin, a 1 count difference between counters is acceptable. the 12 - bit counter is accessed via the 16- bit cnt_snap shot register (see figure 45). if the internal counter of one ADE7912 / ade7913 device d oes not have a value correlated with the values of the counters of the other ADE7912 / ade7913 devices , this means that the adc outputs of one phase are no longer synchronized with the adc outputs from the other phases. the ADE7912 / ade7913 provide two options to resynchronize all the ADE7912 / ade7913 devices : one is to broadcast a write to the 8 - bit sync_snap register with the value 0x01. this action immediately forces all ADE7912 / ade7913 devices to start an adc output cycle simu ltane ously. however, all phases present adc output distortions of various degrees , a function of when a sync_snap = 0x01 write is executed within the current output period. therefore, it is recommended that this command be executed at power - up or after a hardware or software reset. the other option is to compute a new starting value for the internal counter of the ADE7912 / ad e7913 device that is out of synchronization . this value forces the internal counter to start a new adc output cycle , counting down from it , and end simultane ously with the other counters of the other ADE7912 / ade7913 devices . the 12 - bit value is stored in two 8 - bit registers , counter1 and counter0 (see figure 46 ). counter0 contains the least significant eight bits and must be written first. counter1 contains the four most significant bits and must be written after counter0. the advantage of this opti on compared to writing sync_snap = 0x01 is that only the adc outputs of out of sync phases are affected. the other phases already in synchronization remain unaffected . as a general rule, it is recommended that the synchronization of the ADE7912 / ade7913 devices be verified every couple of seconds. figure 46 . counter start value communicated using two 8 - bit registers consider the example shown in figure 44: the phase a, phase b , and phase c counters of three ADE7912 / ade7913 devices are shown for the meter configuration shown i n figure 35 . all three phases are out of synchronization. it is desir able to synchronize the phase a and phase b ADE7912 / ade7913 devices with the phase c ADE7912 / ade7913 , which i s considered the reference because it gener ates the dready signal . ADE7912 c ade7913 c ADE7912 b ade7913 b ADE7912 a ade7913 a c 0 c 0 c 0 c a dready adc cycle 0 adc cycle 1 adc cycle 2 adc cycle 3 adc cycle 4 c b c c sync_snap = 0x02 c a , c b , c c are read all ADE7912/ade7913s are in sync ADE7912 b /ade7913 b counter starts from a new value ADE7912 a /ade7913 a counter starts from a new value new c a = c 0 + c c ? c a is written (c c < c a ) new c b = c c ? c b is written (c c > c b ) * * 111 15-022 0 7 8 counter value 11 0000 12 15 111 15-023 8-bit unsigned number 0 7 0 7 8 counter[11:0] 0 7 counter1[7:0] 11 counter0[7:0] 3 4 0000 4-bit unsigned number 111 15-024
ADE7912/ade7913 data sheet rev. 0 | page 30 of 44 when the dready active low pulses are generated, execute t he following steps immediately after the output registers ( i w v, v1wv, v2wv, adc_crc , status0 , and cnt_snapshot ) are read: 1. adc cycle 0. disable the protection of the configuration registers by setting the l ock register to 0x9c (s ee the protecting the integrity of configuration registers section) . set t he 8 - bit register sync_snap to 0x0 2 using a write broadcast command. the c a , c b , and c c values of the three counters are latched and stored in the cnt_snap shot register of each device . 2. adc cycle 1. the ADE7912 / ade7913 counter s (c a , c b , and c c ) latched at cycle 0 are read in burst mode from the cnt_snapshot reg ister together with the i w v, v 1 w v, v2 wv, adc_crc , and status0 registers. 3. adc cycle 2. because c a > c c , the following equation can be written: * 0 aa c cccc +=+ where * a c is the new value that must be determined. the new initial counter value , a0c * a cccc ?+= , is written into the phase a ADE7912 / ade7913 (labeled ADE7912 a / ade7913 a in figure 44) in two consecutive 8- bit writes to the counter0 and counter1 registers. the p hase a ADE7912 / ade7913 device is in sync hroniza - tion with the phase c ADE7912 / ade7913 starting with adc cycle 4. because c b < c c , the following equation can be written: * bbc ccc += where * b c is the new value that must be determined. the n ew initial counter value , bc * b ccc ?= , is written into the phase b ADE7912/ ade7913 in two consecutive 8 - bit writes to the counter0 and counter1 registers. p hase b ADE7912 / ade7913 is in synchronization with the phase c ad e7912 / ade7913 starting with adc cycle 4. as demonstrated, if the latched value of the counter on the reference phase x is c x and the initial value of the counter is c 0 (see table 1 ), the new value of the counter on ph ase y that is required to bring phase y in synchronization to phase x is as follows : if c y > c x , then y xy cccc ?+= 0 * (1 0) if c y c x , then yxy ccc ?= * (11 ) 4. adc cycle 3 . the phase a and phase b ADE7912 / ade7913 counters start counting down b ased on the counter1 and c ounter0 values written during adc cycle 2. 5. adc cycle 4. all ADE7912 / ade7913 devices generate adc outputs synchronously. to verify this, as a good program ming practice, read the counters again so that the sync_snap = 0x02 command is executed one more time. 6. adc cycle 5. the ADE7912 / ade7913 counters (c a , c b , and c c ), latched after the sync_snap = 0x 0 2 command , are stored in the cnt_snap shot regist er and are read in burst mode . they show the same value , 1 lsb, which means 1 clkin cycle ( 244 ns for clkin = 4.096 mhz) . c c = c a 1 = c b 1 7. ree nable protection of the configuration registers by setting the l ock register to 0xca (s ee the protecting the integrity of configuration registers section) . the 1 lsb error may appear because clkin, the internal clock of the ADE7912 / ade7913 , is asynchronous to the serial port clock generated by the microcontroller and is used to write the counter1 and counter0 values during adc cycle 2. the emi reduction scheme managed by the emi_ctrl regis - ter (see the dc - to - dc converter section for details) re quires that the ADE7912 / ade7913 devices of the meter system provide coherent samples. this emi reduction scheme ensures that one ADE7912 / ade7913 device does not generate the pwm signals required to manage the dc - to - dc converter at the same mo ment as another ADE7912 / ade7913 . the 1 lsb error in the counter synchronization means that at least two ADE7912 / ade7913 devices generate pwm signals simultaneously for one clkin cycle and the emi reduction scheme may be affected . although the re are no guarantees, both synchronization procedures outlined in this section can be repeated until c c = c a = c b .
data sheet ADE7912/ade7913 rev. 0 | page 31 of 44 p ower m anagement dc - to - dc c onverter the dc - to - dc converter section of the ADE7912 / ade7913 works on principles that are common to most modern power supply designs. vdd power is supplied to an oscilla ting circuit that drives the primary side of a chip scale air core transformer. power is transferred to the secondary side , where it is rectified to a 3.3 v dc voltage. th is voltage is then supplied to the adc side section through a 2.5 v ldo regulator. the internal dc - to - dc converter state of the ADE7912 / ade7913 is controlled by the input , vdd . in normal operation mode, ma intain v dd between 2.97 v and 3.6 3 v. the block diagram of the isolated dc - to - dc converter is shown in figure 47 . the ADE7912/ ade7913 primary supply voltage vdd input supplies an alternative current (ac) source. the ac signal passes through a chip scale air core transformer , and it is transferred to the secondary side. a rectifier then produces the isolated power supply , vdd iso . using another chip scale air core transformer, a feedback circuit measures vdd iso and passes the information back in to the vdd dom ain, where a pwm control block controls the ac source to maintain vdd iso at 3.3 v. figure 47 . isolated dc - to- dc converter block diagram the pwm control block works at a clkin/4 ( 1 .024 mhz ) clock , and every half period generates a pwm pulse to the ac source ( see figure 48). figure 48 . pwm control block generates pulse s based on a 1 .024 mhz clock every time a pwm pulse is generated, the ac source transmits very high frequency signals across the isolation barrier to allow efficient power transfer through the small chip scale transformers. this transfer creates high frequency currents that can propagate in the circuit board ground and power planes, causing edge and dipole radiation. the layout guidelines section describes the best pcb layout approach to manage the electromagnetic interference ( emi ) issues. in addition to the layout approach, the 8 - bit emi_ctrl register helps to reduce the emissions generated by the ADE7912 / ade7913 dc - to - dc converter. t he clock that manages the pwm c ontrol block is divided in to eight periodical slots, 0 to 7, as shown in f igure 48. each bit of the emi_ctrl register controls one slot: bit 0 controls slot 0, bit 1 controls slot 1, , bit 7 controls slot 7. when the bit is 1, the default value, the pwm c ontrol block generates a pulse . when the bit is 0, the pwm c ontrol block does not generate a pulse. the recommendation is to have only four of these bits set to 1 while keeping the others at 0 for every ADE7912 / ade7913 used in the system to further reduce the emissions generated by the ADE7912 / ade7913 dc - to - dc converter . if the 3 - phase e nergy meter contains four ADE7912 / ade7913 devices , the ADE7912 / ade7913 devices must first b e synchro - nized (see the synchronizing multiple ADE7912 / ade7913 devices section ). then the emi_ctrl register of every ADE7912 / ade7913 must be initialized. the dc - to - dc converter s of only two ADE7912 / ade7913 devices generate emi at the same moment , lowering the overall emi level of the meter. initialize the emi_ctrl register of the phase a ADE7912 / ade7913 (emi_ctrl a ) to 0x 55 , emi_ctrl b to 0x aa , emi_ctrl c to 0x 55, and emi_ctrl n to 0x aa ( see figure 49) . figure 49 . emi management of a 3- phase meter with four ADE7912 / ade7913 devices if the system contains one, two , or three ADE7912 / ade7913 devices , set four bits to 1 in the emi_ ctrl register according to the approach shown in figure 49, while l eaving some of the slots unused . ac source isolation barrier rectifier vdd iso feedback circuit pwm control to adc block vdd = 3.3v 111 15-025 0 1 2 3 4 5 6 7 0 1 pwm control pulse 1.024mhz clock 111 15-026 0 1 2 3 4 5 6 7 0 1 ADE7912/ade7913 phase a, phase c pwm pulse ADE7912/ade7913 phase b, phase n pwm pulse 1.024mhz clock a, c b, n a, c b, n a, c b, n a, c b, n a, c b, n 11115-027
ADE7912/ade7913 data sheet rev. 0 | page 32 of 44 magnetic field i mmunity the ADE7912 / ade7913 are immune to dc magnetic fields because they use air core transformers . the limitation on the ADE7912 / ade7913 ac magnetic field immunity is set by the condition in which the induced voltage in t he transformer receiving coil is sufficiently large to either falsely set or reset the decoder. the following analysis defines the conditions under which this can occur. the 3.3 v operating condition is examined because it is the nominal supply of the ADE7912 / ade7913 . the pulses at the transformer output have an amplitude greater than 1.0 v. the decoder has a sensing threshol d at about 0.5 v, thus establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by = ? ? ? ? ? ? ?= n n n r dt db v 1 2 ( 12 ) where: b is the ac magnetic field: ( t ) = b sin( t ). n is the number of turns in the receiving coil. r n is the radius of the n th turn in the receiving coi l. given the geometry of the receiving coil in the ADE7912 / ade7913 and an imposed requirement that the induced voltage , v thr , be at most 50% of the 0.5 v margin at the decoder, a maximum allowable external magnetic field, b, is calculated, as shown in equation 13 and figure 50. = = n n n thr rf v b 1 2 2 ( 13 ) w here : f is the frequency of the magnetic field . b is the amplitude of the ac magnetic field . figure 50 . maximum allowable external magnetic field for example, at a magnetic field frequency of 10 k hz, the maximum allowable magnetic field of 2.8 t induces a voltage of 0.25 v at the receiving coil. this voltage is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event occur s during a transmit ted pulse (and is of the worst - case polarity), it reduce s the received pulse from more than 1.0 v to 0.75 v, still well above the 0.5 v sen sing threshold of the decoder. the preceding magnetic field values correspond to specific current magnitudes at given distances from the ADE7912 / ade7913 transformers. = == n n n rf dv d b i 1 2 0 0 2 ( 14 ) where 0 is 4 10 ?7 h/m , the magnetic permeability of the air. figure 51 expresses these allowable current magnitudes as a function of frequency for selected distances. as shown in figure 51 , the ADE7912 / ade7913 are extremely im mune and can be affe cted only by extremely large currents operated at high frequency very close to the component. for the 10 khz example previously noted, a current with a n amplitude of 69 ka placed mm from the ADE7912/ ade7913 is required to affect c omponent operation. note that at combinations of strong magnetic field and high frequ ency, any loops formed by pcb traces can induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. take c are in the layout of such traces to avoid this possibility (see the layout guidelines section) . figure 51 . maximum allowable current for various current -to- ADE7912 / ade7913 spacings 100 10 1 0.1 0.01 0.001 1k 10k 100k 1m 10m 100m magnetic field maximum amplitude (t) frequency (hz) 111 15-028 1000 100 10 1 0.1 0.01 1k 10k 100k 1m 10m 100m maximum allowable current (ka) frequency (hz) 0.005m 1m 0.1m 111 15-029
data sheet ADE7912/ade7913 rev. 0 | page 33 of 44 p ower -up and i nitialization p rocedures at power - up or after a hardware or software reset, the following steps must be executed for a microcontroller managing a system formed by one or multiple ADE7912 / ade7913 devices . power - up procedure for systems with a single ADE7912 / ade7913 for one standalone ADE7912 / ade7913 device managed by a microcontroller, the power - up procedure is as follows (see figure 52 ): 1. connect a crystal between the xtal1 and x tal2 pins. 2. supply v dd to the ADE7912 / ade7913 device . to e nsure that the ADE7912 / ade7913 device starts functioning correctly, the supply must reach 3.3 v ? 10% in less than 23 ms from approx imately a 2. 6 v level. the ADE7912 / ade7913 device start s to function. 3. the dc - to - dc converter power s up and supplies the isolated side of the ADE7912 / ade7913 . the - modulators become functional. this process tak es approximately 100 ms t o execute when the recommended capacitors on the vdd iso , ldo , and ref pins described in table 9 are used. after this time, the isolated side of the ADE7912 / ade7913 is fully functional. 4. to determine when the ADE7912 / ade7913 device is ready to accept commands, read the status0 register until bit 0 ( reset_on ) is cleared to 0 . this h appens approximately 20 ms after the ADE7912 / ade7913 start to function and indicates that the non isolated side of the ADE7912 / ade7913 is fully functional using the default settings . 5. initialize the config register and the emi_ctrl emissions control register . 6. protect the user accessible and internal configuration registers by setting the lock register to 0xca. see the protecting the integrity of configuration registers s ection. 7. when the adc conversion data is available , t he ADE7912 / ade7913 device begins generating a signal that is active low at the clkout/ dready pin for 64 clkin cycles (15.625 s for clkin = 4.096 mhz) . dready functionality is enabled by default at the clkout/ dready pin . 8. the m icrocontroller reads the i w v, v 1 w v, v 2 w v, adc_crc , and status0 registers in spi burst mode (see the spi read operation in burst mode section for more information). note that this power - up procedure also applies in the same way to systems that have multiple ADE7912 / ade7913 devices , each clocked from its own crystal. every ADE7912 / ade7913 device is powered up and started independently. figure 52 . power - up p rocedure f or s ystems w ith o ne or m ultiple ADE7912 / ade7913 devices , each clocked f rom its own crystal ADE7912/ade7913 powered up 3.3v ? 10% 2.6v ADE7912/ade7913 start functioning bit status0[0] (reset_on) cleared to 0 dc-to-dc converter powered up and - modulators functional 0v por timer turned on ADE7912/ade7913 nonisolated side ready ADE7912/ade7913 isolated side ready 23ms 100ms 20ms 111 15-030
ADE7912/ade7913 data sheet rev. 0 | page 34 of 44 power-up procedure for system s with multiple devices that use a single crystal for the polyphase energy meters shown in figure 35, figure 37, and figure 38, in which one single crystal is used, the power-up procedure is as follows (see figure 53): 1. supply v dd to the ADE7912 / ade7913 devices. to ensure that the phase a ADE7912 / ade7913 (labeled ADE7912 a / ade7913 a in figure 53) device starts functioning correctly, the supply must reach 3.3 v ? 10% in less than 23 ms from approximately a 2.6 v level. the ADE7912 a / ade7913 a device is clocked by the 4.096 mhz crystal and starts functioning. the other ADE7912 / ade7913 devices are not clocked yet. 2. the dc-to-dc converter powers up and supplies the isolated side of the ADE7912 a / ade7913 a . the - modulators become functional. this process takes approximately 100 ms to execute when the recommended capacitors on the vdd iso , ldo, and ref pins described in table 9 are used. after this time, the isolated side of the ADE7912 a / ade7913 a is fully functional. 3. to deter m ine w he n t he ADE7912 a / ade7913 a device is ready to accept commands, the status0 register is read until bit 0 (reset_on) is cleared to 0. this happens approximately 20 ms after the ADE7912 a / ade7913 a start to function and indicates that the nonisolated side of the ADE7912 a / ade7913 a is fully functional using the default settings. 4. initialize the config register of the ADE7912 a / ade7913 a with bit 0 (clkout_en) set to 1. the clkout signal is provided at the clkout/ dready pin, and the ADE7912 / ade7913 devices on the other phases are now clocked. 5. initialize emi_ctrl, the emissions control register, of the ADE7912 a / ade7913 a . 6. the dc-to-dc converters of the other ADE7912 / ade7913 devices power up and supply their isolated sides. the - modulators become functional. this process takes approximately 100 ms to execute when the recommended capacitors on the vdd iso , ldo, and ref pins described in table 9 are used. the isolated sides of the ADE7912 / ade7913 devices are now fully functional. 7. read the status0 registers of the other ADE7912 / ade7913 devices until bit 0 (reset_on) is cleared to 0, indicating that their nonisolated sides are fully functional with default settings. this happens approximately 20 ms after the clock signal is provided. 8. initialize the config register of all remaining ADE7912 / ade7913 devices. select one ADE7912 / ade7913 device (phase c ADE7912 / ade7913 in figure 35, figure 37, and figure 38 examples; labeled ADE7912 c / ade7913 c in figure 53) and connect its clkout/ dready pin to an external interrupt i/o pin of the microcontroller. ADE7912 c / ade7913 c must have bit 0 (clkout_en) in the config register left at the default value of 0 to use the dready functionality of the clkout/ dready pin. 9. initialize emi_ctrl, the emissions control register, of all remaining ADE7912 / ade7913 devices. 10. execute a sync_snap = 0x01 write broadcast to synchro- nize all the ADE7912/ ade7913 devices of the meter (see the synchronizing multiple ADE7912/ade7913 devices sections). 11. execute a lock = 0xca write broadcast to protect the configuration registers of all ADE7912/ ade7913 devices. see the protecting the integrity of configuration registers section. 12. every couple of seconds, disable the protection of the configuration registers, execute a sync_snap = 0x02 write broadcast to read the cnt_snapshot register of every ADE7912 / ade7913 , and verify if resynchronization is necessary. resynchronize the ADE7912 / ade7913 devices that are out of synchronization (see the synchronizing multiple ADE7912/ade7913 devices section) and then reenable the protection of the configuration registers.
data sheet ADE7912/ade7913 rev. 0 | page 35 of 44 figure 53 . power - up procedure f or systems w ith multiple ADE7912 / ade7913 devices ; only phase a ADE7912 / ade7913 are c locked from a c rystal figure 54 . power - up procedure f or systems w ith multiple ADE7912 / ade7913 devices clocked f rom a micro controller all ADE7912/ade7913s powered up ADE7912 a / ade7913 a por timer turned on ADE7912 a / ade7913 a start functioning ADE7912 a / ade7913 a bit status0[0] (reset_on) cleared to 0 ADE7912 b /ade7913 b , ADE7912 c /ade7913 c , ADE7912 n /ade7913 n dc-to-dc converters powered up and - modulators functional microprocessor sets ADE7912 a / ade7913 a bit config[0] to 1. ADE7912 a / ade7913 a generate clkout ADE7912 a /ade7913 a dc-to-dc converter powered up and its - modulators functional ADE7912 b /ade7913 b , ADE7912 c /ade7913 c , ADE7912 n /ade7913 n bit status0[0] (reset_on) cleared to 0 3.3v ? 10% 2.6v 0v ADE7912 b /ade7913 b , ADE7912 c /ade7913 c , ADE7912 n /ade7913 n , nonisolated side ready ADE7912 b /ade7913 b , ADE7912 c /ade7913 c , ADE7912 n /ade7913 n , isolated side ready ADE7912 a /ade7913 a nonisolated side ready ADE7912 a /ade7913 a isolated side ready 23ms 100ms 100ms 20ms 20ms 111 15-031 all ADE7912/ ade7913s powered up ADE7912/ ade7913s por timers turned on microprocessor generates clock to ADE7912/ade7913s ADE7912/ade7913s bit status0[0] (reset_on) cleared to 0 ADE7912/ade7913s dc-to-dc converters powered up and - modulators functional 3.3v ? 10% 2.6v 0v all ADE7912/ ade7913s nonisolated side ready all ADE7912/ ade7913s isolated side ready 20ms 100ms 111 15-032
ADE7912/ade7913 data sheet rev. 0 | page 36 of 44 power - up procedure for systems with multiple devices that use clock generated from microcontroller for poly phase energy meters in which the microcontroller generates the clock signal used by all ADE7912 / ade7913 devices (see figure 36) , the power - up procedure is as follows : 1. supply v dd to the ADE7912 / ade7913 devices . to ensure that the ADE7912 / ade7913 devic es start functioning correctly, the supply must reach 3.3 v ? 10% in less than 23 ms from a pproximately a 2. 6 v level. 2. generate the clock signal from the microcontroller to all ADE7912 / ade7913 devices . 3. the dc - to - dc converters power up and supply the isolated side of the ADE7912 / ade7913 devices. the - modulators become functional. this process takes approximately 100 ms to execute when the recommended capacitors on the vdd iso , ldo , and ref pins described in table 9 are used. after this time, the isolated sides of the ADE7912 / ade7913 devices are fully functional. 4. read the status0 registers of the ADE7912 / ade7913 devi ces until bit 0 (reset_on) is cleared to 0, indicating that the nonisolated side of the ADE7912 / ade7913 devices is fully functional with default settings. this happens approximately 20 ms after the clock signal is provided. 5. initialize the config register of the ADE7912 / ade7913 devices with bit 0 (clkout_en) cleared to 0 to avoid generating an unnecessary clock at the clkout/ dready pin. select one ade79 12/ ade7913 device ( phase c ADE7912 / ade7913 in figure 36 , for example) and connect its clkout/ dready pin to an external interrupt i/o pin of the microcontroller. 6. initialize emi_ctr l, the emissions control register , of all ADE7912 / ade7913 devices . 7. execute a sync_snap = 0x01 write broadcast to synchroni ze all the ADE7912 / ade7913 devices of the meter (see the synchronizing multiple ADE7912 / ade7913 devices sections for details). 8. execute a lock = 0xca write broadcast to protect the configuration register s of all ade79 12/ ade7913 devices . see the protecting the integrity of configuration registers sec tion. 9. every couple of seconds, disable the registers protection, execute a sync_snap = 0x02 write broadcast to read the counter1 and counter0 registers of every ADE7912 / ade7913 , and verify if resynchronization is necessary. resynchronize the ADE7912 / ade7913 devices that are out of sync hronization (see the synchronizing multiple ADE7912 / ade7913 devices section ) and then re enable protection of the configuration register s. hardware reset the ADE7912 / ade7913 do not have a dedicated reset pin . instead, while the sclk pin is receiving the serial clock, the cs and mosi pins can be kept low by executing a spi broad cast write operation in which the lines are kept low for 64 sclk cycles. this is equiv alent to sending eight bytes equal to 0x00 to the ADE7912 / ade7913 to accomplish a hardware reset. during a hardware reset, all the registers are set to their default values and the dc - to - dc converter is shut down. this procedure can be done simultaneously for all ADE7912 / ade7913 devices in a polyphase energy meter. at the end of the reset period, the ADE7912 / ade79 13 clears bit 0 (reset_on) to 0 in the status0 register. at this point, one of the procedures described in the power - up and initialization procedures section must be followed to initialize the ADE7912 / ade7913 devices correctly. software r eset bit 6 (swrst) in the config register manages the software reset functionality. the default value of this bit is 0. if this bit is set to 1, the ADE7912 / ade7913 enter the software reset state. in this state, all the internal registers are re set to their default values. the dc - to - dc converter continues to function. when the software reset ends, bit 6 (swrst) in the config regis ter clears automatically to 0 and bit 0 ( reset_on ) in the status0 register is cleared to 0 . if the configuration registers are protected using a lock = 0xca register write, first unlock the registers by writing lock = 0x9c and then write to the config register by setting bit 6 (swrst) to 1 to start a software reset. at this point, one of the procedures described in th e power - up and initialization procedures section must be followed to initialize the ADE7912 / ade7913 correctly . power - down mode there are situations in which the adcs of the ADE7912 / ade7913 do not need to function and it is desirable to lower the cu rrent consumption of the device . when set to 1, bit 2 (pwrdwn_en) in the config register turns off the dc - to - dc converter and shuts down the - modulators . although the ADE7912 / ade7913 configuration registers maintain their values, the iwv, v1wv , and v2wv adc output registers are in an undefined state. if pwrdwn_en is cleared to 0, the default value, the dc - to - dc converter is functional and the - modulator s are active. if the microcontroller generates the clock to all ADE7912 / ade7913 device s ( the configuration shown in figure 36 ), the current consumption can be further reduced by shutting down the clock. the ADE7912 / ade7913 stop functioning. wh en the clock is restarted, as a good programming practice, execute a hardware reset to restart the ADE7912 / ade7913 . in systems in which the clkout / dready pin of one ADE7912 / ade7913 device is used to clock other ADE7912 / ade7913 devices ( the configuration shown in figure 35, figure 37, and figure 38 ), lo wer current consumption of the ADE7912 / ade7913 devices can be achieved by clearing bit 0 (clkout_en) to 0 in the config register.
data sheet ADE7912/ade7913 rev. 0 | page 37 of 44 layout guidelines figure 20 shows the test circuit of the ADE7912 / ade7913 . the test circuit contains three ADE7912 / ade7913 devices together with the surrounding circuitry required to sense the phase currents and voltages in a 3 - phase system. the ADE7912 / ade7913 devices are managed by a microcontroller using the spi interface. the microcontroller is not shown in the schematic. figure 20 replicates the schematic of the ade7913 evaluation board (see the ade7913 evaluation b oard section ) . figure 55 and figure 56 show a proposed layout of a printed circuit board (pcb) with two layers that have the components placed on the top of the board only. follow these layout guidelines to create a low noise design with higher immunity to emc influences. note that the layout is cropped from a board containing other circuitry besides the three ade7913 devices. the layout of an ADE7912 - based meter is very similar to the one designed for the ade7913 . the only difference is the absence of the v2p voltage channel , which means the absence of the related circuitry: the resistor divider and the protection diodes. the primary supply voltage is supplied at vdd, pin 19. p lace a 10 f decoupling capacitor and a 100 nf ceramic decoupling capacitor between the vdd pin and gnd, pin 20. the 10 f capacitor must be placed in close proximity to the part, but the ceramic capacitor must be placed closer to the ADE7912 / ade7913 because it dec ouples the high frequency noise . use a 10 f capacitor and a 100 nf ceramic capacitor to decouple vdd iso , pin 1, from gnd iso , pin 2. apply the same rules in the placement of these capacitors as for the vdd pin . use a 4.7 f capacitor and a 100 nf , ceramic capacitor to decouple ldo, pin 8, and ref, pin 9, from gnd iso , pin 10. use the same rules in the placement of t hese capacitors as for the vdd pin . note that the ADE7912 / ade7913 isolated ground point is one of the shunt poles. this po int is directly connected to gnd iso , pin 10. there is no need to connect the shunt ground pole to gnd iso , pin 2. pin 2 is internally connected to pin 10. the crystal load capacitors must be placed closest to the ADE7912 / ade7913 , whereas the crystal can be placed in close proximity. note that the bottom layer extends the ground of the primary side below the ADE7912 / ade7913 and the related circuitry. a distance of a t least 8 mm is maintained on the bottom layer between the input p ins on the board and the primary side ground plane. figure 55 . 2- layer circuit board: top layer 111 15-043
ADE7912/ade7913 data sheet rev. 0 | page 38 of 44 figure 56 . 2- layer circuit board: bottom layer figure 57 . 4- layer circuit board: top layer 8mm 111 15-044 8mm 111 15-045
data sheet ADE7912/ade7913 rev. 0 | page 39 of 44 figure 58 . 4- layer circuit board: bottom layer figure 59 . stitching capacitors created by 4 - layer pcb if a 4 - layer pcb is used, additional stitching capacitors can be created. on the top layer, all components placed on the isolated secondary side are surrounded by a ground plane connected to gnd iso , pin 10 (see figure 57 ). layer 2 (see figure 60) replicates the bottom layer of the 2 - layer circuit board app roach, extending the ground of the primary side below the ADE7912 / ade7913 and the related circuitry. layer 3 (see figure 61 ) replicates the ground plane of the top layer. the bottom layer does not have the ground of the primary side below the ade79 12/ ade7913 and the related circuitry as in the 2 - layer circuit board approach because the corresponding stitching capacitor created with layer 3 does not have any effect in reducing the emi ssions. the structure of the stitching capacitors created by a 4 - layer pcb is shown in figure 59 . the isolated ground plane of the top layer creates t he 10 pf capacitor (c12) with the primary side ground plane placed on layer 2. in a similar manner, the 400 pf (c23) capacitor is created between layer 2 and layer 3. these capacitances have an important role in reducing the emissions generated by the ADE7912 / ade7913 dc - to - dc converter. ade7913 evaluation board an evaluation board built upon the ade7913 allows users to quickly evaluate this ic. it is used in conjunction with the system demonstration platform ( e va l - sdp - cb1z ). order both the ade7913 evaluation board and the system demonstration platform to evaluate the ade7913 . visit www.analog.com/ade7913 for details. ADE7912 / ade7913 version bits[2:0] (version) in the status1 register identify the version of the ADE7912 / ade7913 . 111 15-046 ADE7912/ade7913 primary side ground plane on top layer isolated side ground plane on top layer primary side ground plane on layer 2 isolated side ground plane on layer 3 primary side ground plane on bottom layer c12 c23 28mils = 0.7112mm 28mils = 0.7112mm 4mils = 0.1016mm 8mm 1mm 111 15-047
ADE7912/ade7913 data sheet rev. 0 | page 40 of 44 figure 60 . 4- layer circuit board: layer 2 figure 61 . 4- layer circuit board: layer 3 111 15-048 111 15-049
data sheet ADE7912/ade7913 rev. 0 | page 41 of 44 register list in table 13 to table 20 , r means a register can be read, and w means a register can be written. u means an unsigned register, and s means a signed register in twos complement format. table 13 . register list address register name r/w bit length type default value description 0 x0 iwv r 24 s 0x000000 instantaneous value of current i. 0x 1 v 1 wv r 24 s 0x000000 instantaneous value of voltage v 1 . 0x 2 v2 wv r 24 s 0x000000 instantaneous value of voltage v 2 . 0x 3 reserved r 24 s 0x000000 reserved. this location always reads 0x000000. 0x 4 adc_crc r 16 u n/a crc value of iwv, v 1 wv , and v 2 wv registers. see the adc output values crc section for details. 0x 5 ctrl_crc r 16 u n/a crc value of configuration registers. see the crc of configuration registers for details. 0x 6 reserved r 16 s 0x0000 reserved. this location always reads 0x0000. 0x 7 cnt_snapshot r 16 u 0x00 snapshot value of the counter used in synchronization operation. see table 14 and the synchronizing multiple ADE7912 / ade7913 devices section for details. 0x 8 config r/w 8 u 0 configuration register. see table 15 for details. 0x 9 status0 r 8 u 0x01 status register. see table 16 for details. 0xa lock w 8 u 0x00 memory protection register. see the protecting the integrity of configuration registers section and table 17 for details. 0xb s ync _ snap w 8 u 0x00 synchronization register. see table 18 for details. 0xc counter0 r/w 8 u n/a contains the least significant eight bits of the internal synchronizatio n counter. 0xd counter1 r/w 8 u n/a counter1[3:0] bits contain the most significant four bits of the internal synchronization counter. see the synchronizing multiple ADE7912 / ade7913 devices section for details. 0xe emi_ctrl r/w 8 u 0xf f emi control register. manages the pwm control block of the isolated dc -to - dc converter to reduce emi emissions (see table 19 and the dc -to - dc converter section for details). 0xf status1 r 8 u 0x00 status register. see table 20 for details. 0x10, 0x11 reserved r/w 8 u 0x00 for proper operation, do not write to t hese registers . 0x1 2 , 0x13 reserved r 8 u 0x00 reserved registers. 0x14 reserved no functionality assigned at this address. 0x15, 0x16, 0x17 reserved r 8 u 0x00 reserved registers. 0x18 tempos r 8 s n/a temperature sensor offset . see the temperature sensor section for more information. table 14. cnt_snapshot register (address 0x7 ) bit location bit name default value description 11:0 counter 0x000 snapshot value of the counter used in synchronization operation. 15:12 reserved 0000 reserved. these bits do not represent any functionality.
ADE7912/ade7913 data sheet rev. 0 | page 42 of 44 table 15. config register (address 0x8) bit location bit name default value description 0 clkout_en 0 enables clkout functionality at the clkout/ dready pin. when clkout_en = 0, the default value, dready functionality is enabled. when clkout_en = 1, clkout functionality is enabled . 1 reserved 0 reserved. this bit does not manage any functionality. 2 pwrdwn_en 0 shuts down the dc -to - dc converter. when pwrdwn_en = 0, the default value, the dc -to - dc converter is functional and the - modulator s are active. when pwrdwn_en = 1, the dc -to - dc converter is turned off and the - modulator s are shut down. 3 temp_en 0 this bit selects the second voltage channel measurement. when the temp_en bit is set to 0, the default value, the voltage between the v 2 p and v m pins is measured. when this bit is 1, the internal temperature sensor is measured ( see the temperature sensor section for more information ) . in the case of the ADE7912 , the internal temperature sensor is always measured , and this bit does not have any significance . 5: 4 adc_freq 00 these bits select the adc output frequency. 00 = 8 k hz, 125 s period. 01 = 4 k hz, 250 s period. 10 = 2 k hz, 500 s period. 11 = 1 k hz, 1 ms period. 6 swrst 0 when this bit is set to 1, a software reset is initiated. this b it clears itself to 0 after one clkin cycle. 7 bw 0 selects t he bandwidth of the digital low - pass filter of the adc. when bw = 0, the default value, the bandwidth is 3.3 khz. when bw = 1, the bandwidth is 2 khz. the bandwidth data is for clkin = 4.096 mhz and an adc output frequency of 8 khz. see the analog -to - digital con version section for details on how clkin and the adc output frequency influence the bandwidth selection. table 16. status0 register (address 0x 9 ) bit location bit name default value description 0 reset_ on 1 during reset, the reset_ on bit is set to 1. when the reset ends and the ADE7912 / ade7913 are ready to be configured, the reset_ on bit is cleared to 0. 1 crc_stat 0 if the crc of the configuration registers changes value, crc_stat bit is set to 1. 2 ic_prot 0 if the configuration registers are not protected, this bit is 0. after the configuration register s are protected (lock register = 0xca) , this bit is set to 1. 7:3 reserved 0 reserved. these bits do not represent any functionality. table 17. lock register (address 0x a ) bit location bit name default value description 7:0 lock_key 00000000 when the lock_key bits are equal to 0xca, protection of the configuration registers is enabled. when the lock_key bits are equal to 0x9c, the protection is disabled and the configuration registers can be written. this is a write only register. if the address location is read, the value is 0x00. table 18. sync_snap register (address 0xb) bit location bit name default value description 0 sync 0 when the sync bit is set to 1 via a broadcast spi write operation, the ADE7912 / ade7913 devices in the system generate adc outputs in the same exact moment. the bit clears itself back to 0 after one clkin cycle. see the synchronizing multiple ADE7912 / ade7913 devices section for more details. 1 snap 0 when snap is set to 1 via a broadcast spi write operation, the internal counters of the ADE7912 / ade7913 devices in the system are latched. the bit clears itself back to 0 after one clkin cycle. see the synchronizing multiple ADE7912 / ade7913 devices section for more details. 7: 2 reserved 0 reserved. these bits do not represent any functionality.
data sheet ADE7912/ade7913 rev. 0 | page 43 of 44 table 19. emi_ctrl register (address 0x e ) bit location bit name default value description 0 slot0 1 control s the pwm c ontrol block pulse dur ing slot 0 of the clkin/4 clock (see the dc -to - dc converte r section for details). 1 slot1 1 control s the pwm c ontrol block pulse during slot 1 of the clkin/4 clock. 2 slot2 1 control s the pwm c ontrol block pulse during slot 2 of the clkin/4 clock. 3 slot3 1 control s the pwm c ontrol block pulse during slot 3 of the clkin/4 clock. 4 slot4 1 control s the pwm c ontrol block pulse during slot 4 of the clkin/4 clock. 5 slot5 1 control s the pwm c ontrol block pulse during slot 5 of the clkin/4 clock. 6 slot6 1 control s the pwm c ontrol block pulse during slot 6 of the clkin/4 clock. 7 slot7 1 control s the pwm c ontrol block pulse during slot 7 of the clkin/4 clock. table 20. status1 register (address 0xf) bit location bit name default value description 2:0 version 0 the ADE7912 / ade7913 version number. 3 adc_na 0 if the adc outputs are not accessed during one adc output period, the adc_na bit is set to 1. when the status1 register is read, the bit is cleared to 0. 6 : 4 reserved 0 reserved. these bits do not represent any functionality. 7 reserved 0 reserved. internal functionality is associated with this bit.
ADE7912/ade7913 data sheet rev. 0 | page 44 of 44 outline dimensions figure 62 . 20 - lead standard small outline package , with increased creepage [soic_ic ] wide body (ri - 20 - 1) dimensions shown in millimeters ordering guide model 1 , 2 temperature range package description package option ADE7912ariz ? 40c to +85c 20 - lead soic_ic ri -20 -1 ADE7912ariz -rl ? 40c to +85c 20 - lead soic_ic, 13 tape and reel ri -20 -1 ade7913a ri z ? 40c to +85c 20 - lead soic_ ic ri -20 -1 ade7913a ri z -rl ? 40c to +85c 2 0 - lead soic_ ic , 13 tape and reel r i -20 -1 eval - ade7913ebz evaluation board eval - sdp - cb1z evaluation system controller board 1 z = rohs compliant part. 2 the eval - sdp - cb1z is the controller board that manages the eval - ade7913ebz evaluation board. both boards must be ordered together. 1 1-15-20 1 1- a 20 1 1 10 1 se a ting plane coplanarit y 0.1 1.27 bsc 15.40 15.30 15.20 7.60 7.50 7.40 2.64 2.54 2.44 1.01 0.76 0.51 0.30 0.20 0.10 10.51 10.31 10. 1 1 0.46 0.36 2.44 2.24 pin 1 mark 1.93 ref 8 0 0.32 0.23 0.71 0.50 0.31 45 0.25 bsc gage plane compliant t o jedec s t andards ms-013 ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11115 - 0- 11/13(0)

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